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TL3842DRE4-8 Datasheet(PDF) 10 Page - Texas Instruments |
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TL3842DRE4-8 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 18 page TL284x, TL384x CURRENT-MODE PWM CONTROLLERS SLVS038F – JANUARY 1989 – REVISED FEBRUARY 2003 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION shutdown technique The PWM controller (see Figure 7) can be shut down by two methods: either raise the voltage at ISENSE above 1 V or pull the COMP terminal below a voltage two diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output remains low until the next clock cycle after the shutdown condition at the COMP or ISENSE terminal is removed. In one example, an externally latched shutdown can be accomplished by adding an SCR that resets by cycling VCC below the lower UVLO threshold. At this point, the reference turns off, allowing the SCR to reset. 330 Ω 1 k Ω 500 Ω To Current-Sense Resistor REF ISENSE Shutdown Shutdown COMP Figure 7. Shutdown Techniques A fraction of the oscillator ramp can be summed resistively with the current-sense signal to provide slope compensation for converters requiring duty cycles over 50% (see Figure 8). Note that capacitor C forms a filter with R2 to suppress the leading-edge switch spikes. RT 0.1 µF CT R1 R2 ISENSE RSENSE C REF RT/CT ISENSE Figure 8. Slope Compensation |
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