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TAS5121DKD Datasheet(PDF) 10 Page - Texas Instruments |
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TAS5121DKD Datasheet(HTML) 10 Page - Texas Instruments |
10 / 18 page TAS5121 SLES086A − NOVEMBER 2003 − REVISED MARCH 2004 www.ti.com 10 THEORY OF OPERATION POWER SUPPLIES This power device requires only two power supply voltages, GVDD_x and PVDD_x. GVDD_x is the gate drive supply for the device, which is usually supplied from an external 12-V power supply. GVDD_x is also connected to an internal LDR that regulates the GVDD_x voltage down to the logic power supply, 3.3 V, for the TAS5121 internal logic blocks. Each GVDD_x pin is decoupled to system ground by a 1- µF capacitor. PVDD_x is the H-bridge power supply. Two power pins are provided for each half-bridge due to the high current density. It is important to follow the circuit and PCB layout recommendations for the design of the PVDD_x connection. For component suggestions, see the Typical System Configuration section in this document. For layout guidelines, see the reference design layout for the TAS5121. Following these recommendations is important because they influence key system parameters such as EMI, idle current, and audio performance. When GVDD_x is applied, while RESET is held low, the error latches are cleared, SHUTDOWN is set high, and the outputs are held in a high-impedance state. The bootstrap capacitor is charged by the current path through the internal bootstrap diode and external resistors placed on the PCB from each OUT_x pin to ground. A subsequent section describes the charging of the bootstrap capacitor. Ideally, PVDD_x is applied after GVDD_x. When GVDD_x and PVDD_x are applied, the TAS5121 is ready for operation. PWM input signals can then be applied any time during the power-on sequence, but they must be active and stable before RESET is set high. RECOMMENDATIONS FOR POWERING UP RESET GVDD PVDD_X PWM_xP > 1 ms > 1 ms The following table describes the input conditions and the output states of the device: INPUTS OUTPUTS Condition RESET PWM _AP PWM _BP SHUT- DOWN OUT_ A OUT_ B Condition Description X X X 0 Hi-Z Hi-Z Shutdown 0 X X 1 Hi-Z Hi-Z Reset 1 0 0 1 GND GND 1 0 0 1 PVDD PVDD Normal 1 0 1 1 GND PVDD Normal 1 1 1 1 PVDD PVDD Reserved After the previously mentioned conditions are met, the device output begins. If PWM_AP is equal to a high and PMW_BP is equal to a low, the high-side MOSFET in the A half-bridge of the output H-bridge conducts while the low-side MOSFET in the A half-bridge is not conducting. Because the source of the high-side MOSFET is referenced to the drain of the low-side MOSFET, a bootstrapped gate drive is used to eliminate the need for additional high-voltage power supplies. Under the above condition, the opposite is true for the B half-bridge of the output H-bridge. The low-side MOSFET in B half-bridge conducts while the high-side MOSFET is not conducting; therefore, the load connected between the OUT_A and OUT_B pins has PVDD applied to it from the A side while ground is applied from the B side for the period of time PWM_AP is high and PWM_BP is low. Furthermore, when the PWM signals change to the condition where PWM_AP is low and PWM_BP is high, the opposite condition exists. A constant high level is not permitted on the PWM inputs. This condition causes the bootstrap capacitors to discharge and can cause device damage. |
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