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EP1C6T144C8ES Datasheet(PDF) 54 Page - Altera Corporation |
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EP1C6T144C8ES Datasheet(HTML) 54 Page - Altera Corporation |
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54 / 104 page  2–48 Altera Corporation Preliminary January 2007 Cyclone Device Handbook, Volume 1 A programmable delay chain on each DQS pin allows for either a 90° phase shift (for DDR SDRAM), or a 72° phase shift (for FCRAM) which automatically center-aligns input DQS synchronization signals within the data window of their corresponding DQ data signals. The phase-shifted DQS signals drive the global clock network. This global DQS signal clocks DQ signals on internal LE registers. These DQS delay elements combine with the PLL’s clocking and phase shift ability to provide a complete hardware solution for interfacing to high-speed memory. The clock phase shift allows the PLL to clock the DQ output enable and output paths. The designer should use the following guidelines to meet 133 MHz performance for DDR SDRAM and FCRAM interfaces: ■ The DQS signal must be in the middle of the DQ group it clocks ■ Resynchronize the incoming data to the logic array clock using successive LE registers or FIFO buffers ■ LE registers must be placed in the LAB adjacent to the DQ I/O pin column it is fed by Figure 2–34 illustrates DDR SDRAM and FCRAM interfacing from the I/O through the dedicated circuitry to the logic array. EP1C6 144-pin TQFP 4 32 240-pin PQFP 4 32 256-pin FineLine BGA 4 32 EP1C12 240-pin PQFP 4 32 256-pin FineLine BGA 4 32 324-pin FineLine BGA 8 64 EP1C20 324-pin FineLine BGA 8 64 400-pin FineLine BGA 8 64 Note to Table 2–10: (1) EP1C3 devices in the 100-pin TQFP package do not have any DQ pin groups in I/O bank 1. Table 2–10. DQ Pin Groups (Part 2 of 2) Device Package Number of × 8 DQ Pin Groups Total DQ Pin Count |
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