Electronic Components Datasheet Search
  English  ▼

Delete All
ON OFF
ALLDATASHEET.COM

X  

Preview PDF HTML

ZL30409 Datasheet(PDF) 1 Page - Zarlink Semiconductor Inc

Part No. ZL30409
Description  T1/E1 System Synchronizer with Stratum 3 Holdover
Download  32 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Maker  ZARLINK [Zarlink Semiconductor Inc]
Homepage  http://www.zarlink.com
Logo 

ZL30409 Datasheet(HTML) 1 Page - Zarlink Semiconductor Inc

 
Zoom Inzoom in Zoom Outzoom out
 1 / 32 page
background image
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.
Features
• Supports Telcordia GR-1244-CORE Stratum 4
timing for DS1 interfaces
• Supports ETSI ETS 300 011, TBR 4, TBR 12 and
TBR 13 timing for E1 interfaces
• Selectable 19.44 MHz, 2.048 MHz, 1.544 MHz or
8 kHz input reference signals
• Provides C1.5, C2, C4, C6, C8, C16, and C19
(STS-3/OC3 clock divided by 8) output clock
signals
• Provides 5 styles of 8 KHz framing pulses
• Holdover frequency accuracy of 0.05 PPM
• Holdover indication
• Attenuates wander from 1.9 Hz
• Fast lock mode
• Provides Time Interval Error (TIE) correction
• Accepts reference inputs from two independent
sources
• JTAG Boundary Scan
Applications
• Synchronization and timing control for multitrunk
T1,E1 and STS-3/OC3 systems
• ST-BUS clock and frame pulse sources
Description
The ZL30409 T1/E1 System Synchronizer contains a
digital phase-locked loop (DPLL), which provides timing
and synchronization signals for multitrunk T1 and E1
primary rate transmission links.
The ZL30409 generates ST-BUS clock and framing
signals that are phase locked to either a 19.44 MHz,
2.048 MHz, 1.544 MHz, or 8 kHz input reference.
April 2006
Ordering Information
ZL30409/DDE
48 Pin SSOP
Tubes
ZL30409/DDF
48 Pin SSOP
Tape & Reel
ZL30409DDE1 48 Pin SSOP*
Tubes, Bake & Drypack
ZL30409DDF1 48 Pin SSOP*
Tape & Reel,
Bake & Drypack
*Pb Free Matte Tin
-40
°C to +85°C
ZL30409
T1/E1 System Synchronizer
with Stratum 3 Holdover
Data Sheet
Figure 1 - Functional Block Diagram
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
IEEE
1149.1a
Reference
Select
Feedback
TIE
Corrector
Enable
Control State Machine
State
Select
State
Select
Frequency
Select
MUX
Input
Impairment
Monitor
Output
Interface
Circuit
Reference
Select
MUX
TIE
Corrector
Circuit
MS1 MS2
FS1
FS2
TCK
SEC
RST
RSEL
VDD
GND
TCLR
C1.5o
C19o
C2o
C4o
C8o
C16o
F0o
F8o
F16o
OSCo
OSCi
Master Clock
TDO
PRI
TDI
TMS
TRST
C6o
RSP
TSP
HOLDOVER
FLOCK
PCCi
LOCK
Virtual
Reference
Selected
Reference
DPLL


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32 


Datasheet Download




Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ]  

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Alldatasheet API   |   Link Exchange   |   Manufacturer List
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn