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ZL30409 Datasheet(PDF) 6 Page - Zarlink Semiconductor Inc

Part No. ZL30409
Description  T1/E1 System Synchronizer with Stratum 3 Holdover
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Maker  ZARLINK [Zarlink Semiconductor Inc]
Homepage  http://www.zarlink.com
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ZL30409 Datasheet(HTML) 6 Page - Zarlink Semiconductor Inc

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ZL30409
Data Sheet
6
Zarlink Semiconductor Inc.
Figure 3 - TIE Corrector Circuit
As shown in Figure 3, the TIE Corrector Circuit receives one of the two reference (PRI or SEC) signals, passes the
signal through a programmable delay line, and uses this delayed signal as an internal virtual reference, which is
input to the DPLL. Therefore, the virtual reference is a delayed version of the selected reference.
During a switch from one reference to the other, the State Machine first changes the mode of the device
from Normal to Holdover. In Holdover Mode, the DPLL no longer uses the virtual reference signal, but generates an
accurate clock signal using storage techniques. The Compare Circuit then measures the phase delay between the
current phase (feedback signal) and the phase of the new reference signal. This delay value is passed to the
Programmable Delay Circuit (See Figure 3). The new virtual reference signal is now at the same phase position as
the previous reference signal would have been if the reference switch not taken place. The State Machine then
returns the device to Normal Mode.
The DPLL now uses the new virtual reference signal, and since no phase step took place at the input of the DPLL,
no phase step occurs at the output of the DPLL. In other words, reference switching will not create a phase change
at the input of the DPLL, or at the output of the DPLL.
Since internal delay circuitry maintains the alignment between the old virtual reference and the new virtual
reference, a phase error may exist between the selected input reference signal and the output signal of the DPLL.
This phase error is a function of the difference in phase between the two input reference signals during reference
rearrangements. Each time a reference switch is made, the delay between input signal and output signal will
change. The value of this delay is the accumulation of the error measured during each reference switch.
The programmable delay circuit can be zeroed by applying a logic low pulse to the TIE Circuit Reset (TCLR) pin. A
minimum reset pulse width is 300 ns. This results in a phase alignment between the input reference signal and the
output signal as shown in Figure 14.
Digital Phase Lock Loop (DPLL)
As shown in Figure 4, the DPLL of the ZL30409 consists of a Phase Detector, Loop Filter, Digitally Controlled
Oscillator, and a Control Circuit.
Programmable
Delay Circuit
Control Signal
Delay Value
TCLR
Resets Delay
Compare
Circuit
TIE Corrector
Enable
from
State Machine
Control
Circuit
Feedback
Signal from
Frequency
Select MUX
PRI or SEC
from
Reference
Select Mux
Virtual
Reference
to DPLL


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