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TAS5012PFB Datasheet(PDF) 6 Page - Texas Instruments |
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TAS5012PFB Datasheet(HTML) 6 Page - Texas Instruments |
6 / 19 page TAS5012 SLES006A – SEPTEMBER 2001 – REVISED DECEMBER 2001 6 www.ti.com functional description (continued) digital interpolation filter The 24-bit high-performance linear phase FIR interpolation filter up-samples the input digital data at a rate of two times (quad speed mode = 176.4 kHz or 192 kHz), four times (double speed mode = 88.2 kHz or 96 kHz), or eight times (normal mode = 32 kHz, 44.1 kHz, or 48 kHz) the incoming sample rate. This filter provides very low pass-band ripple and optimized time domain transient response for accurate music reproduction. digital PWM modulator The interpolation filter output is sent to the modulator. This modulator consists of a high performance fourth order digital noise shaper and a PCM-to-PWM converter. Following the noise shaper, the PCM signal is fed into a very low distortion PCM-to-PWM conversion block, buffered, and output from the chip. The modulation scheme is based on a 2-state control of the H-bridge output. control, status, and operational modes The TAS5012 control section consists of several control-input pins. Three serial mode pins (MOD0, MOD1, and MOD2) are provided to select various serial data formats. During normal operating conditions if any of the MOD0, MOD1, or MOD2 pins changes state, a reset sequence is initiated. Also provided are separate power-down (PDN), reset (RESET), and mute (MUTE) pins. power up At power up the VALID_L and VALID_R pins are asserted low and the PWM outputs go to the hard mute state in which the P outputs are held low and the M outputs are held high. Following initialization, the TAS5012 comes up in the operational state (differential PWM audio). There are two cases of power-up timing. The first case is shown in Figure 1 with RESET preceding PDN. The second case is shown in Figure 2 with PDN preceding RESET. Initialization Time = 100 ms max RESET PDN VALID_L VALID_R Figure 1. Power-Up Timing (RESET Preceding PDN) Initialization Time = 5 ms max RESET PDN Greater Than 16 MCLK Periods VALID_L VALID_R Figure 2. Power-Up Timing (PDN Preceding RESET) |
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