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SST36VF1602C-70-4I-B3KE Datasheet(PDF) 4 Page - Silicon Storage Technology, Inc

Part # SST36VF1602C-70-4I-B3KE
Description  16 Mbit (x8/x16) Dual-Bank Flash Memory
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Manufacturer  SST [Silicon Storage Technology, Inc]
Direct Link  http://www.sst.com/
Logo SST - Silicon Storage Technology, Inc

SST36VF1602C-70-4I-B3KE Datasheet(HTML) 4 Page - Silicon Storage Technology, Inc

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Data Sheet
16 Mbit Dual-Bank Flash Memory
SST36VF1601C / SST36VF1602C
©2006 Silicon Storage Technology, Inc.
S71249-06-000
1/06
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating “1”s
and “0”s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling. The device is then ready for the next opera-
tion. The toggle bit is valid after the rising edge of the fourth
WE# (or CE#) pulse for Program operations. For Sector-,
Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the
rising edge of sixth WE# (or CE#) pulse. DQ6 will be set to
“1” if a Read operation is attempted on an Erase-sus-
pended Sector/Block. If Program operation is initiated in a
sector/block not selected in Erase-Suspend mode, DQ6 will
toggle.
An additional Toggle Bit is available on DQ2, which can be
used in conjunction with DQ6 to check whether a particular
sector is being actively erased or erase-suspended. Table 1
shows detailed status bit information. The Toggle Bit (DQ2)
is valid after the rising edge of the last WE# (or CE#) pulse
of a Write operation. See Figure 11 for Toggle Bit timing
diagram and Figure 24 for a flowchart.
Note: DQ7, DQ6, and DQ2 require a valid address when reading
status information.
Data Protection
The devices provide both hardware and software features
to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Hardware Block Protection
The devices provide hardware block protection which pro-
tects the outermost 8 KWord in the larger bank. The block
is protected when WP# is held low. See Figures 1, 2, 3,
and 4 for Block-Protection location.
A user can disable block protection by driving WP# high.
This allows data to be erased or programmed into the pro-
tected sectors. WP# must be held high prior to issuing the
Write command and remain stable until after the entire
Write operation has completed.
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the
devices to read array data. When the RST# pin is held low
for at least TRP, any in-progress operation will terminate and
return to Read mode (see Figure 20). When no internal
Program/Erase operation is in progress, a minimum period
of TRHR is required after RST# is driven high before a valid
Read can take place (see Figure 19).
The Erase operation that has been interrupted needs to be
re-initiated after the device resumes normal operation
mode to ensure data integrity.
Software Data Protection (SDP)
These devices provide the JEDEC standard Software Data
Protection scheme for all data alteration operations, i.e.,
Program and Erase. Any Program operation requires the
inclusion of the three-byte sequence. The three-byte load
sequence is used to initiate the Program operation, provid-
ing optimal protection from inadvertent Write operations,
e.g., during the system power-up or power-down. Any
Erase operation requires the inclusion of the six-byte
sequence. The devices are shipped with the Software Data
Protection permanently enabled. See Table 5 for the spe-
cific software command codes. During SDP command
sequence, invalid commands will abort the device to Read
mode within TRC. The contents of DQ15-DQ8 can be VIL or
VIH, but no other value during any SDP command
sequence.
TABLE
1: WRITE OPERATION STATUS
Status
DQ7
DQ6
DQ2
RY/BY#
Normal
Operation
Standard
Program
DQ7#
Toggle
No Toggle
0
Standard
Erase
0
Toggle
Toggle
0
Erase-
Suspend
Mode
Read From
Erase
Suspended
Sector/Block
1
1
Toggle
1
Read From
Non-Erase
Suspended
Sector/Block
Data
Data
Data
1
Program
DQ7#
Toggle
No Toggle
0
T1.2 1249


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