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SST34HF3244C-70-4E-LSE Datasheet(PDF) 5 Page - Silicon Storage Technology, Inc |
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SST34HF3244C-70-4E-LSE Datasheet(HTML) 5 Page - Silicon Storage Technology, Inc |
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5 / 40 page  Data Sheet 32 Mbit Concurrent SuperFlash + 4 Mbit SRAM ComboMemory SST34HF3244C 5 ©2006 Silicon Storage Technology, Inc. S71282-02-000 8/06 Toggle Bits (DQ6 and DQ2) During the internal Program or Erase operation, any con- secutive attempts to read DQ6 will produce alternating “1”s and “0”s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next opera- tion. The toggle bit is valid after the rising edge of the fourth WE# (or BEF#) pulse for Program operations. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or BEF#) pulse. DQ6 will be set to “1” if a Read operation is attempted on an Erase-sus- pended Sector/Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle. An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check whether a particular sector is being actively erased or erase-suspended. Table 1 shows detailed status bit information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or BEF#) pulse of a Write operation. See Figure 11 for Toggle Bit tim- ing diagram and Figure 23 for a flowchart. Note: DQ7, DQ6, and DQ2 require a valid address when reading status information. The address must be in the bank where the operation is in progress in order to read the operation sta- tus. If the address is pointing to a different bank (not busy), the device will output array data. Data Protection The SST34HF3244C provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or BEF# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, BEF# high, or WE# high will inhibit the Write operation. This prevents inadvert- ent writes during power-up or power-down. Hardware Block Protection The SST34HF3244C provide a hardware block protection which protects the outermost 8 KWord/16 KByte in Bank 1. The block is protected when WP# is held low. When WP# is held low and a Block-Erase command is issued to the protected block, the data in the outermost 8 KWord/16 KByte section will be protected. The rest of the block will be erased. See Table 3 for Block-Protection location. A user can disable block protection by driving WP# high thus allowing erase or program of data into the protected sectors. WP# must be held high prior to issuing the write command and remain stable until after the entire Write operation has completed. If WP# is left floating, it is inter- nally held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program and Erase operations on that block. Hardware Reset (RST#) The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode (see Figure 19). When no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST# is driven high before a valid Read can take place (see Figure 18). The Erase operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity. See Figures 18 and 19 for timing diagrams. TABLE 1: Write Operation Status Status DQ7 DQ6 DQ2 RY/BY# Normal Operation Standard Program DQ7# Toggle No Toggle 0 Standard Erase 0 Toggle Toggle 0 Erase- Suspend Mode Read From Erase Suspended Sector/Block 1 1 Toggle 1 Read From Non-Erase Suspended Sector/Block Data Data Data 1 Program DQ7# Toggle No Toggle 0 T1.1 1282 |
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