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SST34HF3244 Datasheet(PDF) 7 Page - Silicon Storage Technology, Inc |
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SST34HF3244 Datasheet(HTML) 7 Page - Silicon Storage Technology, Inc |
7 / 41 page Data Sheet 32 Mbit Concurrent SuperFlash + 4/8 Mbit PSRAM ComboMemory SST34HF3244 / SST34HF3282 / SST34HF3284 7 ©2006 Silicon Storage Technology, Inc. S71335-00-000 8/06 Product Identification The Product Identification mode identifies the device as either SST34HF3282 or SST34HF32x4 and manufacturer as SST. This mode may be accessed by software opera- tions only. The hardware device ID Read operation, which is typically used by programmers cannot be used on this device because of the shared lines between flash and PSRAM in the multi-chip package. Therefore, application of high voltage to pin A9 may damage this device. Users may use the software Product Identification operation to identify the part (i.e., using the device ID) when using multiple man- ufacturers in the same socket. For details, see Tables 5 and 6 for software operation, Figure 15 for the Software ID Entry and Read timing diagram and Figure 24 for the ID Entry command sequence flowchart. Note: BK = Bank Address (A20-A18) Product Identification Mode Exit/ CFI Mode Exit In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accom- plished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit command is ignored during an internal Program or Erase operation. See Table 6 for software command codes, Fig- ure 17 for timing waveform and Figure 24 for a flowchart. PSRAM Operation With BES1# low, BES2 and BEF# high, the SST34HF32xx operate as either 256K x16 or 512K x16 CMOS PSRAM, with fully static operation requiring no external clocks or tim- ing strobes. The SST34HF32xx PSRAM is mapped into the first 512 KWord address space. When BES1#, BEF# are high and BES2 is low, all memory banks are dese- lected and the device enters standby. Read and Write cycle times are equal. The control signals UBS# and LBS# pro- vide access to the upper data byte and lower data byte. See Table 5 for x16 PSRAM Read and Write data byte control modes of operation. PSRAM Read The PSRAM Read operation of the SST34HF32xx is con- trolled by OE# and BES1#, both have to be low with WE# and BES2 high for the system to obtain data from the out- puts. BES1# and BES2 are used for PSRAM bank selec- tion. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to the Read cycle timing diagram, Figure 4, for further details. PSRAM Write The PSRAM Write operation of the SST34HF32xx is con- trolled by WE# and BES1#, both have to be low, BES2 must be high for the system to write to the PSRAM. During the Word-Write operation, the addresses and data are ref- erenced to the rising edge of either BES1#, WE#, or the falling edge of BES2 whichever occurs first. The write time is measured from the last falling edge of BES#1 or WE# or the rising edge of BES2 to the first rising edge of BES1#, or WE# or the falling edge of BES2. Refer to the Write cycle timing diagrams, Figures 5 and 6, for further details. TABLE 2: Product Identification ADDRESS DATA Manufacturer’s ID BK0000H 00BFH Device ID SST34HF3282 BK0001H 7351H SST34HF3244/3284 BK0001H 7353H T2.0 1335 |
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