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TAS5010PFBR Datasheet(PDF) 5 Page - Texas Instruments |
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TAS5010PFBR Datasheet(HTML) 5 Page - Texas Instruments |
5 / 19 page TAS5010 SLAS328 – SEPTEMBER 2001 5 www.ti.com functional description serial audio port The serial audio port consists of a shift clock (SCLK pin), a left/right frame synchronization clock (LRCLK pin), and a data input (SDIN pin). The serial audio port supports standard serial PCM formats (Fs = 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4kHz, or 192kHz) stereo. See serial interface formats section. system clocks—master mode and slave mode The TAS5010 allows multiple system clocking schemes. In this document, master mode indicates that the TAS5010 provides system clocks to other parts of the system (M_S=1). Audio system clocks of frequency 256Fs MCLK_OUT, 64 Fs SCLK, and Fs LRCLK are output from this device when it is configured in master mode. Slave mode indicates that a system master other than the TAS5010 provides system clocks (LRCLK, SCLK, and MCLK_IN) to the TAS5010 (M_S = 0). The TAS5010 operates with LRCLK and SCLK synchronized to MCLK. TAS5010 does not require any specific phase relationship between LRCLK and MCLK, but there must be synchronization. In the slave mode MCLK_OUT is driven low. Table 1 shows all the possible master and slave modes. When operating in quad mode (Fs = 176.4kHz or 192 kHz), the device works in slave mode only with MCLK_IN = 128 Fs. oscillator/sampling frequency The sampling frequency is determined by the crystal (master mode) or master clock in (slave mode) which should be either 11.2896 MHz (Fs = 44.1 kHz) or 12.288 MHz (Fs = 48 kHz). Twice the normal sampling frequency can be selected by using the DBSPD pin which allows usage of Fs = 88.2 kHz or Fs = 96 kHz. In the double-speed slave mode (DBSPD = 1, M_S = 0), the external clock input is either 22.5796 MHz (Fs = 88.2 kHz) or 24.576 MHz (Fs = 96 kHz). Table 1 explains the proper clock selection. Table 1. Oscillator, External Clock, and PLL Functions DESCRIPTION M_S DBSPD XTL_IN (MHz)† MCLK_IN (MHz)‡ SCLK (MHz)¶ LRCLK (kHz)¶ MCLK_OUT (MHz)# Master, normal speed 1 0 11.2896 — 2.8224 44.1 11.2896 Master, normal speed 1 0 12.288 — 3.072 48 12.288 Master, double speed 1 1 — 22.5792§ 5.6448 88.2 22.5792 Master, double speed 1 1 — 24.576§ 6.144 96 24.576 Slave, normal speed 0 0 — 11.2896§ 2.8224 44.1 Digital GND Slave, normal speed 0 0 — 12.288§ 3.072 48 Digital GND Slave, double speed 0 1 — 22.5792§ 5.6448 88.2 Digital GND Slave, double speed 0 1 — 24.576§ 6.144 96 Digital GND Slave, quad speed|| 0 0 — 22.5792§ 11.2896 176.4 Digital GND Slave, quad speed|| 0 0 — 24.576§ 12.288 192 Digital GND † Either a crystal oscillator or an external clock of the specified frequency can be connected to XTL_IN. ‡ MCLK_IN tied low when input to XTL_IN is provided; XTL_IN tied low when MCLK_IN is provided. § External MCLK connected to MCLK_IN input ¶ SCLK and LRCLK are outputs when M_S=1, inputs when M_S=0. # MCLK_OUT is driven low when M_S=0. || Quad speed mode is detected automatically. phase-locked loop (PLL)/clock generation A low jitter PLL is incorporated for internal use. Connections for the PLL external loop filter are provided as PLL_FLT_RET and PLL_FLT_OUT. If the PLL loses lock, the PWM output status pins (VALID_L and VALID_R) go low. Note that VALID_L and VALID_R can go low for other conditions as well. See error status reporting section. |
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