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MT9074 Datasheet(PDF) 89 Page - Zarlink Semiconductor Inc |
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MT9074 Datasheet(HTML) 89 Page - Zarlink Semiconductor Inc |
89 / 151 page MT9074 Data Sheet 89 Zarlink Semiconductor Inc. Per Channel Receive Signaling (T1 and E1 mode) (Pages 9 and 0AH) Page 09H, addresses 10000 to 11111, and page 1AH addresses 10000 to 10111 contain the Receive Signaling Control Words for DS1 channels 1 to 16 and 17 to 24 respectively. Table 76 illustrates the mapping between the addresses of these pages and the DS1 channel numbers. Table 77 describes bit allocation within each of these registers. 4LTSL Local Time Slot Loopback. If one, the corresponding transmit time slot is looped to the corresponding receive time slot. This transmit time slot will also be present on the transmit DS1 stream. If zero, this loopback is disabled. 3TTST Transmit Test. If one, a test signal, either digital milliwatt (when control bit ADSEQ is one) or PRBS (Z15-1) (ADSEQ is zero), will be transmitted in the corresponding DS1 time slot. More than one time slot may be activated at once. If zero, the test signal will not be connected to the corresponding time slot. 2RTST Receive Test. If one, the corresponding DSTo time slot will be used for testing. If control bit ADSEQ is one, a digital milliwatt signal will be transmitted into the DSTo channel. If ADSEQ is zero, the receive channel will be connected to the PRBS (215 - 1) detector. 1RPSIG Serial Signaling Enable. If set low, the transmit signaling buffer for the equivalent DS1 channel will be sourced from the ST-BUS channel on CSTi associated with it. If set high the transmit signaling RAM must be programmed via the microport. 0CC Clear Channel. When set high no robbed bit signaling is inserted in the equivalent transmit DS1 channel. When set low robbed bit signaling is included in every 6th channel. Page 9 Address: 012345678910 11 12 13 14 15 Equivalent DS1 channel 12345678910 11 12 13 14 15 16 Page A Address: 012345678910 11 12 13 14 15 Equivalent DS1 channel 17 18 19 20 21 22 23 24 xxxxxxxx Table 76 - Page 9, A Address Mapping to DS1 Channels (T1) Bit Name Functional Description Table 75 - Per Time Slot Control Words (Pages 7 and 8) (T1) |
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