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TSC2101 Datasheet(PDF) 13 Page - Texas Instruments |
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TSC2101 Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 93 page  TSC2101 SLAS392D− JUNE 2003 − REVISED MAY 2005 www.ti.com 13 th(WS) ts(WS) ts(DI) th(DI) td(DO−BCLK) WCLK BCLK SDOUT SDIN tH(BCLK) tL(BCLK) tP(BCLK) ts(WS) th(WS) Figure 4. DSP Timing in Slave Mode Typical Timing Requirements (see Figure 4) PARAMETER(1) IOVDD = 1.1 V IOVDD = 3.3 V UNITS PARAMETER(1) MIN MAX MIN MAX UNITS tH(BCLK) BCLK high period 40 35 ns tL(BCLK) BCLK low period 40 35 ns tP(BCLK) BCLK period 80 80 ns ts(WS) WCLK setup 6 6 ns th(WS) WCLK hold 6 6 ns td(DO−BCLK) BCLK to DOUT delay 30 15 ns ts(DI) SDIN setup 6 6 ns th(DI) SDIN hold 6 6 ns tr Rise time 5 4 ns tf Fall time 5 4 ns (1) These parameters are based on characterization and are not tested in production. |
Similar Part No. - TSC2101_07 |
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Similar Description - TSC2101_07 |
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