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SST34HF162G-70-4C-L3KE Datasheet(PDF) 2 Page - Silicon Storage Technology, Inc |
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SST34HF162G-70-4C-L3KE Datasheet(HTML) 2 Page - Silicon Storage Technology, Inc |
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2 / 31 page  2 Preliminary Specifications 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162G / SST34HF164G ©2004 Silicon Storage Technology, Inc. S71276-00-000 11/04 Designed, manufactured, and tested for applications requir- ing low power and small form factor, the SST34HF16xG are offered in both commercial and extended temperatures and a small footprint package to meet board space con- straint requirements. See Figure 2 for pin assignments. Device Operation The SST34HF16xG use BES# and BEF# to control opera- tion of either the flash or the SRAM memory bank. When BEF# is low, the flash bank is activated for Read, Program or Erase operation. When BES# is low the SRAM is acti- vated for Read and Write operation. BEF# and BES# can- not be at low level at the same time. If all bank enable signals are asserted, bus contention will result and the device may suffer permanent damage. All address, data, and control lines are shared by flash and SRAM memory banks which minimizes power consumption and loading. The device goes into standby when BEF# and BES# bank enables are raised to VIHC (Logic High) or when BEF# is high. Concurrent Read/Write Operation The SST34HF16xG provide the unique benefit of being able to read from or write to SRAM, while simultaneously erasing or programming the flash. This allows data alter- ation code to be executed from SRAM, while altering the data in flash. The following table lists all valid states. The device will ignore all SDP commands when an Erase or Program operation is in progress. Note that Product Identification commands use SDP; therefore, these com- mands will also be ignored while an Erase or Program operation is in progress. Flash Read Operation The Read operation of the SST34HF16xG is controlled by BEF# and OE#, both have to be low for the system to obtain data from the outputs. BEF# is used for device selection. When BEF# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either BEF# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 7). Flash Program Operation These devices are programmed on a word-by-word basis. Before programming, one must ensure that the sector which is being programmed is fully erased. The Program operation is accomplished in three steps: 1. Software Data Protection is initiated using the three-byte load sequence. 2. Address and data are loaded. During the Program operation, the addresses are latched on the falling edge of either BEF# or WE#, whichever occurs last. The data is latched on the rising edge of either BEF# or WE#, whichever occurs first. 3. The internal Program operation is initiated after the rising edge of the fourth WE# or BEF#, which- ever occurs first. The Program operation, once ini- tiated, will be completed typically within 7 µs. See Figures 8 and 9 for WE# and BEF# controlled Pro- gram operation timing diagrams and Figure 21 for flow- charts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Pro- gram operation, the host is free to perform additional tasks. Any commands issued during an internal Program opera- tion are ignored. Flash Sector- /Block-Erase Operation These devices offer both Sector-Erase and Block-Erase operations. These operations allow the system to erase the devices on a sector-by-sector (or block-by-block) basis. The sector architecture is based on a uniform sector size of 2 KWord. The Block-Erase mode is based on a uniform block size of 32 KWord. The Sector-Erase operation is initi- ated by executing a six-byte command sequence with a Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. Any commands issued during the Block- or Sector- Erase operation are ignored except Erase-Suspend and Erase-Resume. See Figures 13 and 14 for timing wave- forms. CONCURRENT READ/WRITE STATE TABLE Flash SRAM Program/Erase Read Program/Erase Write |
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