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SST34HF164C-70-4E-LBK Datasheet(PDF) 7 Page - Silicon Storage Technology, Inc |
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SST34HF164C-70-4E-LBK Datasheet(HTML) 7 Page - Silicon Storage Technology, Inc |
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7 / 26 page  Preliminary Specifications 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory SST34HF162C / SST34HF164C 7 ©2004 Silicon Storage Technology, Inc. S71269-01-000 9/04 FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL LBGA (10MM X 12MM) TABLE 3: PIN DESCRIPTION Symbol Pin Name Functions AMSS1 to A0 1. AMS = Most Significant Address AMS = A16 for SST34HF162C and A17 for SST34HF164C Address Inputs To provide flash address, A19-A0. To provide SRAM address, AMSS-A0 DQ15-DQ0 Data Inputs/Outputs To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a flash Erase/Program cycle. The outputs are in tri-state when OE#, BES#, and BEF# are high. BEF# Flash Memory Bank Enable To activate the Flash memory bank when BEF# is low BES# SRAM Memory Bank Enable To activate the SRAM memory bank when BES# is low OE# Output Enable To gate the data output buffers WE# Write Enable To control the Write operations UBS# Upper Byte Control (SRAM) To enable DQ15-DQ8 LBS# Lower Byte Control (SRAM) To enable DQ7-DQ0 VSS Ground VDDF Power Supply (Flash) 2.7-3.3V Power Supply to Flash only VDDS Power Supply (SRAM) 2.7-3.3V Power Supply to SRAM only NC No Connection Unconnected pins T3.1 1269 BES# A10 OE# A11 A13 WE# VSS DQ5 DQ7 A8 A17 VDDS DQ1 DQ2 DQ4 A5 UBS# A16 A1 A0 DQ0 DQ8 BEF# VSS A2 A3 A6 DQ3 DQ10 DQ9 A4 A7 A18 DQ12 VDDF DQ11 A19 NC NC A12 DQ6 DQ13 A9 A14 A15 LBS# DQ15 DQ14 A B C D E F G H SST34HF162C/164C 6 5 4 3 2 1 TOP VIEW (balls facing down) |
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