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SST32HF324C-70-4C-LBK Datasheet(PDF) 2 Page - Silicon Storage Technology, Inc |
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SST32HF324C-70-4C-LBK Datasheet(HTML) 2 Page - Silicon Storage Technology, Inc |
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2 / 28 page  2 Preliminary Specifications Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C ©2005 Silicon Storage Technology, Inc. S71267-02-000 9/05 SuperFlash technology provides fixed Erase and Program times independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hard- ware does not have to be modified or de-rated as is neces- sary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. Device Operation The ComboMemory uses BES# and BEF# to control oper- ation of either the SRAM or the flash memory bank. When BES# is low, the SRAM Bank is activated for Read and Write operation. When BEF# is low the flash bank is acti- vated for Read, Program or Erase operation. BES# and BEF# cannot be at low level at the same time. If BES# and BEF# are both asserted to low level bus contention will result and the device may suffer permanent damage. All address, data, and control lines are shared by SRAM Bank and flash bank which minimizes power consumption and loading. The device goes into standby when both bank enables are high. Concurrent Read/Write Operation The SST32HF324C provide the unique benefit of being able to read from or write to SRAM, while simultaneously erasing or programming the flash. This allows data alter- ation code to be executed from SRAM, while altering the data in flash. See Figure 22 for a flowchart. The following table lists all valid states. The device will ignore all SDP commands when an Erase or Program operation is in progress. Note that Product Identification commands use SDP; therefore, these com- mands will also be ignored while an Erase or Program operation is in progress. Flash Read Operation The Read operation of the SST32HF324C devices is con- trolled by BEF# and OE#. Both have to be low, with WE# high, for the system to obtain data from the outputs. BEF# is used for flash memory bank selection. When BEF# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high imped- ance state when OE# is high. Refer to Figure 5 for further details. Flash Word-Program Operation The flash memory bank of the SST32HF324C devices is programmed on a word-by-word basis. Before Program operations, the memory must be erased first. The Program operation consists of three steps. The first step is the three- byte load sequence for Software Data Protection. The sec- ond step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either BEF# or WE#, whichever occurs last. The data is latched on the rising edge of either BEF# or WE#, whichever occurs last. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or BEF#, whichever occurs first. The Pro- gram operation, once initiated, will be completed, within 10 µs. See Figures 6 and 7 for WE# and BEF# controlled Pro- gram operation timing diagrams and Figure 18 for flow- charts. During the Program operation, the only valid flash Read operations are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any SDP commands loaded during the internal Program operation will be ignored. Flash Sector-/Block-Erase Operation The Flash Sector/Block-Erase operation allows the system to erase the device on a sector-by-sector (or block-by- block) basis. The SST32HF324C offer both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 2 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The Sector- Erase operation is initiated by executing a six-byte com- mand sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The address lines AMS-A11 are used to determine the sector address. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The address lines AMS-A15 are used to determine the block address. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 11 and 12 for timing waveforms. Any commands issued during the Sector- or Block-Erase operation are ignored. CONCURRENT READ/WRITE STATE TABLE Flash SRAM Program/Erase Read Program/Erase Write |
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