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FAN7602MX Datasheet(PDF) 11 Page - Fairchild Semiconductor |
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FAN7602MX Datasheet(HTML) 11 Page - Fairchild Semiconductor |
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11 / 18 page  © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN7602 Rev. 1.0.2 11 Figure 22. CS/FB Pin Voltage Waveforms 4. Burst Mode Block The FAN7602 contains the burst mode block to reduce the power loss at a light load and no load as the FAN7601. A hysteresis comparator senses the offset voltage of the Burst+ for the burst mode as shown in Fig- ure 23. The Burst+ is the sum of the CS/FB voltage and Plimit offset voltage. The FAN7602 enters the burst mode when the offset voltage of the Burst+ is higher than 0.95V and exits the burst mode when the offset voltage is lower than 0.88V. The offset voltage is sensed during the switch off time. Figure 23. Burst Mode Block 5. Protection Block The FAN7602 contains several protection functions to improve system reliability. 5.1 Overload Protection The FAN7602 contains the overload protection function. If the output load is higher than the rated output current, the output voltage drops and the feedback error amplifier is saturated. The offset of the CS/FB voltage represent- ing the feedback information is almost zero. As shown in Figure 24, the CS/FB voltage is compared with 50mV reference when the internal clock signal is high and, if the voltage is lower than 50mV, the OLP timer starts counting. If the OLP condition persists for 22ms, the timer generates the OLP signal. And this protection is reset by the UVLO. The OLP block is enabled after the soft-start finishes. Figure 24. Overload Protection Circuit 5.2 Line Under-Voltage Protection If the input voltage of the converter is lower than the min- imum operating voltage, the converter input current increases too much, causing components failure. There- fore, if the input voltage is low, the converter should be protected. In the FAN7602, the LUVP circuit senses the input voltage using the LUVP pin and, if this voltage is lower than 2V, the LUVP signal is generated. The com- parator has 0.5V hysteresis. If the LUVP signal is gener- ated, the output drive block is shut down, the output voltage feedback loop is saturated, and the OLP works if the LUVP condition persists more than 22ms. Figure 25. Line UVP Circuit 5.3 Latch Protection The latch protection is provided to protect the system against abnormal conditions using the Latch/Plimit pin. The Latch/Plimit pin can be used for the output over- voltage protection and/or other protections. If the Latch/ Plimit pin voltage is made higher than 4V by an external circuit, the IC is shut down. The latch protection is reset when the VCC voltage is lower than 5V. 5.4 Over-Voltage Protection (OVP) If the VCC voltage reaches 19V, the IC shuts down and the OVP protection is reset when the VCC voltage is lower than 5V. 6. Output Drive Block The FAN7602 contains a single totem-pole output stage to drive a power MOSFET. The drive output is capable of up to 450mA sourcing current and 600mA sinking cur- rent with typical rise and fall time of 45ns, 35ns respec- tively with a 1nF load. PWM+ CS/FB GND On Time FB Offset 1V Power Limit Offset (a) Low Power Limit Offset Case PWM+ CS/FB GND On Time FB Offset 1V Power Limit Offset (b) High Power Limit Offset Case FAN7602 Rev. 02 CS /F B De la y Circ u it 3 + − 0.95V /0 .88V Bu rs t+ Offs e t FA N7 60 2 R e v. 0 2 OLP 50mV 22ms Timer Soft-Start Clock CS/FB 3 FAN7602 Rev. 02 2V/1.5V 1 + − LUVP Vin FAN7602 Rev. 02 |
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