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SST32HF32A1-70-4E-LFSE Datasheet(PDF) 2 Page - Silicon Storage Technology, Inc |
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SST32HF32A1-70-4E-LFSE Datasheet(HTML) 2 Page - Silicon Storage Technology, Inc |
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2 / 35 page  2 Preliminary Specifications Multi-Purpose Flash Plus + PSRAM ComboMemory SST32HF32A1 ©2005 Silicon Storage Technology, Inc. S71260-01-000 5/05 The SST32HF32A1 devices are suited for applications that use both flash memory and PSRAM memory to store code or data. For systems requiring low power and small form factor, the SST32HF32A1 devices significantly improve performance and reliability, while lowering power consump- tion, when compared with multiple chip solutions. The SST32HF32A1 inherently use less energy during erase and program than alternative flash technologies. The total energy consumed is a function of the applied voltage, cur- rent, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to pro- gram and has a shorter erase time, the total energy con- sumed during any Erase or Program operation is less than alternative flash technologies. The SuperFlash technology provides fixed Erase and Pro- gram times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Pro- gram cycles. Device Operation The SST32HF32A1 use BES1#, BES2 and BEF# to con- trol operation of either the flash or the PSRAM memory bank. When BEF# is low, the flash bank is activated for Read, Program or Erase operation. When BES1# is low, and BES2 is high the PSRAM is activated for Read and Write operation. BEF# and BES1# cannot be at low level, and BES2 cannot be at high level at the same time. If all bank enable signals are asserted, bus contention will result and the device may suffer permanent damage. All address, data, and control lines are shared by flash and PSRAM memory banks which minimizes power consump- tion and loading. The device goes into standby when BEF# and BES1# bank enables are raised to VIHC (Logic High) or when BEF# is high and BES2 is low. Concurrent Read/Write Operation The SST32HF32A1 provide the unique benefit of being able to read from or write to PSRAM, while simultaneously erasing or programming the flash. This allows data alter- ation code to be executed from PSRAM, while altering the data in flash. See Figure 26 for a flowchart. The following table lists all valid states. The device will ignore all SDP commands when an Erase or Program operation is in progress. Note that Product Identification commands use SDP; therefore, these com- mands will also be ignored while an Erase or Program operation is in progress. Flash Read Operation The Read operation of the SST32HF32A1 devices is con- trolled by BEF# and OE#. Both have to be low, with WE# high, for the system to obtain data from the outputs. BEF# is used for flash memory bank selection. When BEF# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high imped- ance state when OE# is high. Refer to Figure 6 for further details. CONCURRENT READ/WRITE STATE TABLE Flash PSRAM Program/Erase Read Program/Erase Write |
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