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SST25VF040-20-4I-QAE Datasheet(PDF) 7 Page - Silicon Storage Technology, Inc |
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SST25VF040-20-4I-QAE Datasheet(HTML) 7 Page - Silicon Storage Technology, Inc |
7 / 23 page EOL Product Data Sheet 2 Mbit / 4 Mbit SPI Serial Flash SST25VF040 7 ©2006 Silicon Storage Technology, Inc. S71231(04)-00-000 10/06 Block Protection (BP1, BP0) The Block-Protection (BP1, BP0) bits define the size of the memory area, as defined in Table 5, to be software pro- tected against any memory Write (Program or Erase) operations. The Write-Status-Register (WRSR) instruction is used to program the BP1 and BP0 bits as long as WP# is high or the Block-Protect-Lock (BPL) bit is 0. Chip-Erase can only be executed if Block-Protection bits are both 0. After power-up, BP1 and BP0 are set to 1. Block Protection Lock-Down (BPL) WP# pin driven low (VIL), enables the Block-Protection- Lock-Down (BPL) bit. When BPL is set to 1, it prevents any further alteration of the BPL, BP1, and BP0 bits. When the WP# pin is driven high (VIH), the BPL bit has no effect and its value is “Don’t Care”. After power-up, the BPL bit is reset to 0. Auto Address Increment (AAI) The Auto Address Increment Programming-Status bit pro- vides status on whether the device is in AAI programming mode or Byte-Program mode. The default at power up is Byte-Program mode. TABLE 5: Software Status Register Block Protection1 1. Default at power-up for BP1 and BP0 is ‘11’. Protection Level Status Register Bit Protected Memory Area BP1 BP0 2 Mbit 4 Mbit 00 0 None None 1 (1/4 Memory Array) 0 1 030000H-03FFFFH 060000H-07FFFFH 2 (1/2 Memory Array) 1 0 020000H-03FFFFH 040000H-07FFFFH 3 (Full Memory Array) 1 1 000000H-03FFFFH 000000H-07FFFFH T5.0 1231(04) |
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