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CD54HC195 Datasheet(PDF) 4 Page - Texas Instruments

Part No. CD54HC195
Description  High-Speed CMOS Logic 4-Bit Parallel Access Register
Download  13 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

CD54HC195 Datasheet(HTML) 4 Page - Texas Instruments

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4
Prerequisite For Switching Function
PARAMETER
SYMBOL
TEST
CONDITIONS VCC (V)
25oC
-40oC TO 85oC
-55oC TO 125oC
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
Clock Frequency
fMAX
-
2
6-5-4-
MHz
4.5
30
-
25
-
20
-
MHz
6
35
-
29
-
23
-
MHz
MR Pulse Width
tw
-
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14-17
-20-
ns
Clock Pulse Width
tw
-
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14-17
-20-
ns
Set-up Time
J, K, PE to Clock
tSU
-
2
100
-
125
-
150
-
ns
4.5
20
-
25
-
30
-
ns
6
17-21
-26-
ns
Hold Time
J, K, PE to Clock
tH
-
2
3-3-3-
ns
4.5
3-3-3-
ns
6
5
-3-3-
ns
Removal Time,
MR to Clock
tREM
-
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14-17
-20-
ns
Switching Specifications Input tr, tf = 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
VCC (V)
25oC
-40oC TO 85oC
-55oC TO 125oC
UNITS
TYP
MAX
MAX
MAX
HC TYPES
Propagation Delay, CP to
Output
tPLH, tPHL
CL = 50pF
2
-
175
220
265
ns
4.5
-
35
44
53
ns
6
-
30
37
45
ns
Propagation Delay,
MR toOutput
tPLH, tPHL
CL = 50pF
2
-
150
190
225
ns
4.5
-
30
38
45
ns
6
-
26
33
38
ns
Output Transition Times
(Figure 1)
tTLH, tTHL
CL = 50pF
2
-
75
95
110
ns
4.5
-
15
19
22
ns
6
-
13
16
19
ns
Input Capacitance
CIN
--
-
10
10
10
pF
CP to Qn Propagation Delay
tPLH, tPHL
CL = 15pF
5
14
-
-
-
ns
MR to Qn
tPHL
CL = 15pF
5
13
-
-
-
ns
Maximum Clock Frequency
fMAX
CL = 15pF
5
50
-
-
-
MHz
Power Dissipation
Capacitance (Notes 2, 3)
CPD
CL = 15pF
45
-
-
-
pF
NOTES:
2. CPD is used to determine the dynamic power consumption, per flip-flop.
3. PD =VCC
2 f
i + ∑ (CL VCC
2 +f
O) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
CD54HC195, CD74HC195


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