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K8D1716UTC-TC07 Datasheet(PDF) 7 Page - Samsung semiconductor |
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K8D1716UTC-TC07 Datasheet(HTML) 7 Page - Samsung semiconductor |
7 / 41 page FLASH MEMORY K8D1716UTC / K8D1716UBC Revision 1.0 December 2004 7 PRODUCT INTRODUCTION Table 7. Operations Table Operation CE OE WE BYTE WP/ ACC A9 A6 A1 A0 DQ15/ A-1 DQ8/ DQ14 DQ0/ DQ7 RESET Read word L L H H L/H A9 A6 A1 A0 DQ15 DOUT DOUT H byte L L H L A9 A6 A1 A0 A-1 High-Z DOUT H Stand-by Vcc ± 0.3V X X X (2) X X X X High-Z High-Z High-Z (2) Output Disable L H H X L/H X X X X High-Z High-Z High-Z H Reset X X X X L/H X X X X High-Z High-Z High-Z L Write word L H L H (4) A9 A6 A1 A0 DIN DIN DIN H byte L H L L A9 A6 A1 A0 A-1 High-Z DIN H Enable Block Group Protect (3) LH L X L/H X L H L X X DIN VID Enable Block Group Unprotect (3) LH L X (4) X H H L X X DIN VID Temporary Block Group XX X X (4) X X X X X X X VID Auto Select Manufacturer ID (5) LL H X L/H VID LL L X X Code(See Table 9) H Auto Select Device Code (5) LL H X L/H VID LL H X X Code(See Table 9) H Notes : 1. L = VIL (Low), H = VIH (High), VID = 8.5V~12.5V, DIN = Data in, DOUT = Data out, X = Don't care. 2. WP/ACC and RESET pin are asserted at Vcc ±0.3 V or Vss±0.3 V in the Stand-by mode. 3. Addresses must be composed of the Block address (A12 - A19). The Block Protect and Unprotect operations may be implemented via programming equipment too. Refer to the "Block Group Protection and Unprotection". 4. If WP/ACC=VIL, the two outermost boot blocks is protected. If WP/ACC=VIH, the two outermost boot block protection depends on whether those blocks were last protected or unprotected using the method described in "Block Group Protection and Unprotection". If WP/ACC=VHH, all blocks will be temporarily unprotected. 5. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 9. The K8D1716U is a 16Mbit (16,777,216 bits) NOR-type Flash memory. The device features single voltage power supply operating within the range of 2.7V to 3.6V. The device is programmed by using the Channel Hot Electron (CHE) injection mechanism which is used to program EPROMs. The device is erased electrically by using Fowler-Nordheim tunneling mechanism. To provide highly flex- ible erase and program capability, the device adapts a block memory architecture that divides its memory array into 39 blocks (64- Kbyte x 31 , 8-Kbyte x 8). Programming is done in units of 8 bits (Byte) or 16 bits (Word). All bits of data in one or multiple blocks can be erased simultaneously when the device executes the erase operation. To prevent the device from accidental erasing or over-writ- ing the programmed data, 39 memory blocks can be hardware protected by the block group. Byte/Word modes are available for read operation. These modes can be selected via BYTE pin. The device provides read access times of 70ns, 80ns and 90ns supporting high speed microprocessors to operate without any wait states. The command set of K8D1716U is fully compatible with standard Flash devices. The device is controlled by chip enable (CE), output enable (OE) and write enable (WE). Device operations are executed by selective command codes. The command codes to be com- bined wih addresses and data are sequentially written to the command registers using microprocessor write timing. The command codes serve as inputs to an internal state machine which controls the program/erase circuitry. Register contents also internally latch addresses and data necessary to execute the program and erase operations. The K8D1716U is implemented with Internal Program/ Erase Algorithms to execute the program/erase operations. The Internal Program/Erase Algorithms are invoked by program/erase command sequences. The Internal Program Algorithm automatically programs and verifies data at specified addresses. The Internal Erase Algorithm automatically pre-programs the memory cell which is not programmed and then executes the erase operation. The K8D1716U has means to indicate the status of completion of program/erase operations. The status can be indicated via the RY/BY pin, Data polling of DQ7, or the Toggle bit (DQ6). Once the operations have been completed, the device automatically resets itself to the read mode. The device requires only 14 mA as active read current and 15 mA for program/erase operations. |
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