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MB90347EPF Datasheet(PDF) 64 Page - Fujitsu Component Limited. |
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MB90347EPF Datasheet(HTML) 64 Page - Fujitsu Component Limited. |
64 / 85 page MB90340E Series 64 (9) UART0/1/2/3/4 (TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, fCP ≤ 24 MHz) Notes : • AC characteristic CLK synchronized mode. • CL is the value of the load capacitance applied to the pins during testing. Parameter Symbol Pin Condition Value Unit Remarks Min Max Serial clock cycle time tSCYC SCK0 to SCK4 Internal clock operation output pins are CL = 80 pF + 1 TTL 8 tCP ⎯ ns SCK ↓ → SOT delay time tSLOV SCK0 to SCK4, SOT0 to SOT4 −80 +80 ns Valid SIN → SCK ↑ tIVSH SCK0 to SCK4, SIN0 to SIN4 100 ⎯ ns SCK ↑ → Valid SIN hold time tSHIX SCK0 to SCK4, SIN0 to SIN4 60 ⎯ ns Serial clock “H” pulse width tSHSL SCK0 to SCK4 External clock operation output pins are CL = 80 pF + 1 TTL 4 tCP ⎯ ns Serial clock “L” pulse width tSLSH SCK0 to SCK4 4 tCP ⎯ ns SCK ↓ → SOT delay time tSLOV SCK0 to SCK4, SOT0 to SOT4 ⎯ 150 ns Valid SIN → SCK ↑ tIVSH SCK0 to SCK4, SIN0 to SIN4 60 ⎯ ns SCK ↑ → Valid SIN hold time tSHIX SCK0 to SCK4, SIN0 to SIN4 60 ⎯ ns Internal Shift Clock Mode SCK 2.4 V tSCYC 0.8 V SOT 0.8 V 2.4 V 0.8 V tSLOV SIN VIL VIH tIVSH VIL VIH tSHIX |
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