FLASH MEMORY

10

K9WAG08U1A

K9K8G08U0A K9NBG08U5A

Product Introduction

The K9K8G08U0A is a 8,448Mbit(8,858,370,048 bit) memory organized as 524,288 rows(pages) by 2,112x8 columns. Spare 64x8

columns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommo-

dating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made

up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists

of two NAND structured strings. A NAND structure consists of 32 cells. Total 1,081,344 NAND cells reside in a block. The program

and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array con-

sists of 8,192 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9K8G08U0A.

The K9K8G08U0A has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades

to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by

bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch

Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For

example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block

erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 1056M byte physical space

requires 31 addresses, thereby requiring five cycles for addressing : 2 cycles of column address, 3 cycles of row address, in that

order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase oper-

ation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the

command register. Table 1 defines the specific commands of the K9K8G08U0A.

In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another

page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and

data-input cycles are removed, system performance for solid-state disk application is significantly increased.

The K9WAG08U1A is composed of two K9K8G08U0A chips which are selected separately by each CE1 and CE2 and the

K9NBG08U5A is composed of four K9K8G08U0A chips which are selected seperately by each CE1, CE2, CE3 and CE4. Therefore,

in terms of each CE, the basic operations of K9WAG08U0A and K9NBG08U5A are same with K9K8G08U0A except some AC/DC

charateristics.

Table 1. Command Sets

NOTE : 1. Random Data Input/Output can be executed in a page.

2. Read EDC Status is only available on Copy Back operation.

3. Interleave-operation between two chips is allowed.

It’s prohibited to use F1h and F2h commands for other operations except interleave-operation.

4. Any command between 11h and 81h is prohibited except 70h, F1h, F2h and FFh .

Function

1st Cycle

2nd Cycle

Acceptable Command during Busy

Read

00h

30h

Read for Copy Back

00h

35h

Read ID

90h

-

Reset

FFh

-

O

Page Program

80h

10h

80h---11h

81h---10h

Copy-Back Program

85h

10h

85h---11h

81h---10h

Block Erase

60h

D0h

Two-Plane Block Erase

60h---60h

D0h

85h

-

05h

E0h

Read Status

70h

O

7Bh

O

F1h

O

F2h

O