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SST25LF040A-33-4I-S2AE Datasheet(PDF) 9 Page - Silicon Storage Technology, Inc |
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SST25LF040A-33-4I-S2AE Datasheet(HTML) 9 Page - Silicon Storage Technology, Inc |
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9 / 26 page  Data Sheet 2 Mbit / 4 Mbit SPI Serial Flash SST25LF020A / SST25LF040A 9 ©2006 Silicon Storage Technology, Inc. S71242-05-000 1/06 Read (20 MHz) The Read instruction supports up to 20 MHz, it outputs the data starting from the specified address location. The data output stream is continuous through all addresses until ter- minated by a low to high transition on CE#. The internal address pointer will automatically increment until the high- est memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 4 Mbit density, once the data from address location 7FFFFH had been read, the next output will be from address location 00000H. The Read instruction is initiated by executing an 8-bit com- mand, 03H, followed by address bits [A23-A0]. CE# must remain active low for the duration of the Read cycle. See Figure 4 for the Read sequence. FIGURE 4: READ SEQUENCE 1242 F04.0 CE# SO SI SCK ADD. 01 2 3 4 5 6 7 8 ADD. ADD. 03 HIGH IMPEDANCE 15 16 23 24 31 32 39 40 70 47 48 55 56 63 64 N+2 N+3 N+4 N N+1 DOUT MSB MSB MSB MODE 0 MODE 3 DOUT DOUT DOUT DOUT |
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