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5-232
ClockWorks™
SY10ELT23
SY100ELT23
DESCRIPTION
© 1998 Synergy Semiconductor Corporation
SYNERGY
SEMICONDUCTOR
s 3.0ns typical propagation delay
s <500ps typical output-to-output skew
s Differential PECL outputs
s 24mA TTL outputs
s Flow-through pinouts
s ESD protection of 2000V
s Available in 8-pin SOIC package
The SY10/100ELT23 are dual differential PECL-to-TTL
translators.
Because PECL (Positive ECL) levels are
used, only +5V and ground are required.
The small
outline 8-lead SOIC package and the low skew, dual
gate design of the ELT23 makes it ideal for applications
which require the tranlation of a clock and a data signal.
The ELT23 is available in both ECL standards:
the
10ELT is compatible with positive ECL 10H logic levels,
while the 100ELT is compatible with positive ECL 100K
logic levels.
FEATURES
DUAL DIFFERENTIAL
PECL-to-TTL TRANSLATOR
PIN NAMES
PIN CONFIGURATION/BLOCK DIAGRAM
Pin
Function
Qn
TTL Outputs
Dn
Differential PECL Inputs
VCC
+5.0V Supply
GND
Ground
SOIC
TOP VIEW
ClockWorks™
SY10ELT23
SY100ELT23
1
2
3
4
5
6
7
8
D0
VCC
Q0
GND
Q1
D0
PECL
TTL
D1
D1
Rev.: F
Amendment: /0
Issue Date:
August, 1998