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MB90350E Datasheet(PDF) 2 Page - Fujitsu Component Limited.

Part No. MB90350E
Description  16-bit Proprietary Microcontrollers
Download  85 Pages
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Maker  FUJITSU [Fujitsu Component Limited.]
Homepage  http://edevice.fujitsu.com/fmd/en/index.html
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MB90350E Datasheet(HTML) 2 Page - Fujitsu Component Limited.

 
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MB90350E Series
2
■ FEATURES
• Clock
• Built-in PLL clock frequency multiplication circuit
• Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and
multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 24 MHz).
• Operation by sub clock (up to 50 kHz : 100 kHz oscillation clock divided by two) is allowed (devices without
S-suffix only) .
• Minimum execution time of instruction : 42 ns (when operating with 4-MHz oscillation clock, and 6-time
multiplied PLL clock).
• Built-in clock modulation circuit
• 16 Mbytes CPU memory space
24-bit internal addressing
• Instruction system best suited to controller
• Wide choice of data types (bit, byte, word, and long word)
• Wide choice of addressing modes (23 types)
• Enhanced multiply-divide instructions with sign and RETI instructions
• Clock supervisor (MB90x356x and MB90x357x only)
• Main clock or sub clock is monitored independently.
• Internal CR oscillation clock (100 kHz typical) can be used as sub clock.
• Enhanced high-precision computing with 32-bit accumulator
• Instruction system compatible with high-level language (C language) and multitask
• Employing system stack pointer
• Enhanced various pointer indirect instructions
• Barrel shift instructions
• Increased processing speed
4-byte instruction queue
• Powerful interrupt function
• Powerful 8-level, 34-condition interrupt feature
• Up to 8 channels external interrupts are supported.
• Automatic data transfer function independent of CPU
• Extended intelligent I/O service function (EI2OS) : up to 16 channels
• DMA : up to 16 channels
• Low power consumption (standby) mode
• Sleep mode (a mode that stops CPU operating clock)
• Main timer mode (a timebase timer mode switched from the main clock mode)
• PLL timer mode (a timebase timer mode switched from the PLL clock mode)
• Watch mode (a mode that operates sub clock and watch timer only)
• Stop mode (a mode that stops oscillation clock and sub clock)
• CPU intermittent operation mode
• Process
CMOS technology
• I/O port
• General-purpose input/output port (CMOS output)
- 49 ports (devices without S-suffix : devices that correspond to sub clock)
- 51 ports (devices with S-suffix : devices that do not correspond to sub clock)
(Continued)


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