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ST7L15 Datasheet(PDF) 50 Page - STMicroelectronics |
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ST7L15 Datasheet(HTML) 50 Page - STMicroelectronics |
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50 / 138 page  ST7L15, ST7L19 50/138 11 ON-CHIP PERIPHERALS 11.1 WATCHDOG TIMER (WDG) 11.1.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes the application program to abandon its normal sequence. The Watchdog cir- cuit generates an MCU reset upon expiration of a programmed time period, unless the program re- freshes the counter’s contents before the T6 bit is cleared. 11.1.2 Main Features ■ Programmable free-running downcounter (64 increments of 16000 CPU cycles) ■ Programmable reset ■ Reset (if watchdog activated) when the T6 bit reaches zero ■ Optional reset on HALT instruction (configurable by option byte) ■ Hardware Watchdog selectable by option byte 11.1.3 Functional Description The counter value stored in the CR register (bits T[6:0]) is decremented every 16000 machine cy- cles and the length of the timeout period can be programmed by the user in 64 increments. If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically 30µs. Figure 31. Watchdog Block Diagram RESET WDGA 7-bit DOWNCOUNTER fCPU T6 T0 CLOCK DIVIDER WATCHDOG CONTROL REGISTER (CR) ÷16000 T1 T2 T3 T4 T5 1 |
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