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M41T82 Datasheet(PDF) 21 Page - STMicroelectronics |
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M41T82 Datasheet(HTML) 21 Page - STMicroelectronics |
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21 / 58 page  M41T82 M41T83 Clock operation 21/58 3 Clock operation The M41T8x is driven by a quartz-controlled oscillator with a nominal frequency of 32.768kHz. The accuracy of the Real-Time Clock depends on the frequency of the quartz crystal that is used as the time-base for the RTC. The 8-byte clock register (see Table 2 on page 23 and Table 4 on page 25) is used to both set the clock and to read the date and time from the clock, in binary coded decimal format. Tenths/hundredths of seconds, seconds, minutes, and hours are contained within the first four registers. Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause the oscillator to stop. When reset to a '0' the oscillator restarts within one second (typical). Note: Upon initial power-up, the user should set the ST bit to a '1,' then immediately reset the ST bit to '0.' This provides an additional “kick-start” to the oscillator circuit. Bits D6 and D7 of clock register 03h (century/ hours register) contain the CENTURY bit 0 (CB0) and CENTURY bit 1 (CB1). Bits D0 through D2 of register 04h contain the day (day of week). Registers 05h, 06h, and 07h contain the date (day of month), month, and years. The ninth clock register is the digital calibration register, while the analog calibration register is found at address 12h (these are both described in the clock calibration section). For the M41T83, bit D7 of register 09h (Watchdog register) contains the Oscillator Fail Interrupt Enable bit (OFIE). When the user sets this bit to '1,' any condition which sets the Oscillator Fail bit (OF) (see Section 3.13: Oscillator fail detection on page 43) will also generate an interrupt output. Note: A WRITE to ANY location within the first eight bytes of the clock register (00h-07h), including the ST bit and CB0-CB1 bits will result in an update of the system clock and a reset of the divider chain. This could result in an inadvertent change of the current time. These non-clock related bits should be written prior to setting the clock, and remain unchanged until such time as a new clock time is also written. The eight clock registers may be read one byte at a time, or in a sequential block. Provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. This will prevent a transition of data during the READ. 3.1 Power-down time-stamp When a power failure occurs, the Halt Update bit (HT) will automatically be set to a “1”. This will prevent the clock from updating the clock registers, and will allow the user to read the exact time of the power-down event. Resetting the HT bit to a “0” will allow the clock to update the clock with the current time. For more information, see Application note AN1572. |
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