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A8286 Datasheet(PDF) 5 Page - Allegro MicroSystems

Part No. A8286
Description  Dual LNB Supply and Control Voltage Regulator
Download  19 Pages
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Maker  ALLEGRO [Allegro MicroSystems]
Homepage  http://www.allegromicro.com
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A8286 Datasheet(HTML) 5 Page - Allegro MicroSystems

 
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Dual LNB Supply and Control Voltage Regulator
A8286
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Continued on the next page…
ELECTRICAL CHARACTERISTICS (continued) at T
A = 25°C, VIN = 8 to 16 V, unless noted otherwise
1
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Units
Tone
Tone Frequency
fTONE
20
22
24
kHz
Tone Amplitude, Peak-to-Peak
VTONE(pp)
ILOAD = 0 to 500 mA, CLOAD = 750 nF
400
620
800
mV
Tone Duty Cycle
DCTONE
ILOAD = 0 to 500 mA, CLOAD = 750 nF
40
50
60
%
Tone Rise Time
trTONE
ILOAD = 0 to 500 mA, CLOAD = 750 nF
5
10
15
μs
Tone Fall Time
tfTONE
ILOAD = 0 to 500 mA, CLOAD = 750 nF
5
10
15
μs
EXTM Logic Input
VEXTM(H)
2.0
V
VEXTM(L)
0.8
V
EXTM Input Leakage
IEXTMLKG
–1
1
μA
Tone Detector
Tone Detect Input Amplitude Receive, Peak-to-
Peak
VTDR(pp)
fTONE = 22 kHz sine wave, TMODE = 0
300
mV
Tone Detect Input Amplitude Transmit, Peak-
to-Peak
VTDT(pp)Int
fTONE = 22 kHz sine wave, using internal tone
(options 1 and 2, in figure 2)
400
mV
VTDT(pp)Ext
fTONE = 22 kHz sine wave, using external
tone (options 3 and 4, in figure 2)
300
mV
Tone Reject Input Amplitude, Peak-to-Peak
VTRI(pp)
fTONE = 22 kHz sine wave
100
mV
Frequency Capture
fTDI
600 mVpp sine wave
17.6
26.4
kHz
Input Impedance2
ZTDI
8.6
TDO Output Voltage
VTDO(L)
Tone present, ILOAD = 3 mA
0.4
V
TDO Output Leakage
ITDOLKG
Tone absent, VTDO = 7 V
10
μA
I2C™-Compatible Interface
Logic Input (SDA,SCL) Low Level
VSCL(L)
0.8
V
Logic Input (SDA,SCL) High Level
VSCL(H)
2.0
V
Logic Input Hysteresis
VI2CIHYS
150
mV
Logic Input Current
II2CI
VI2CI = 0 to 7 V
–10
<±1.0
10
μA
Logic Output Voltage SDA and IRQ
Vt2COut(L)
ILOAD = 3 mA
0.4
V
Logic Output Leakage SDA and IRQ
Vt2CLKG
Vt2COut = 0 to 7 V
10
μA
SCL Clock Frequency
fCLK
400
kHz
Output Fall Time
tfI2COut
Vt2COut(H) to Vt2COut(L)
250
ns
Bus Free Time Between Stop/Start
tBUF
1.3
μs
Hold Time Start Condition
tHD:STA
0.6
μs
Setup Time for Start Condition
tSU:STA
0.6
μs


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