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A6280 Datasheet(PDF) 6 Page - Allegro MicroSystems

Part No. A6280
Description  3 Bit Constant Current LED Driver with PWM Control
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Maker  ALLEGRO [Allegro MicroSystems]
Homepage  http://www.allegromicro.com
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A6280 Datasheet(HTML) 6 Page - Allegro MicroSystems

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3 Bit Constant Current LED Driver with PWM Control
A6280
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Functional Description
Cur
Reg2
Cur
Reg1
Latch In
Output
Enable In
Clock In
Out
Rext
0
Out1
Out2
Serial
Data Out
Output
Enable Out
Clock Out
Serial
Data In
Latch Out
GND
Cur
Reg0
Shift Registers
GND
Bit 30
“1”
“0”
Latched Registers
29
30
0
……..
9
10
……..
19
20
……..
Current
Scalar 0
7bits
PWM Counter 2
10 bits
PWM Counter 1
10 bits
PWM Counter 0
10 bits
Clock
Divider
2bits
Unused
1bit
Current
Scalar 1
7bits
Unused
3bit
Vin
Regulator
Vreg
Current
Scalar 2
7bits
Test
Bit
1bit
Test
Bit
1bit
Unused
1bit
Figure 4. Functional Diagram
Shift Registers
The A6280 has a 31 bit shift register that loads data through the
Serial Data In (SDI) pin. The shift registers operate by a first-in
first-out (FIFO) method. The most significant bit (MSB, bit 30)
is the first bit shifted in and the least significant bit (LSB, bit 0)
is shifted in last. The serial data is clocked by a rising edge of
the Clock In (CI) pin. The Serial Data Out (SDO) pin is updated
to the state of bit 30 on the falling edge of the CI pin. This will
prevent any race conditions and erroneous data that might occur
while propagating information through multiple A6280 that are
daisy chained together. The contents of the shift registers will
continue to propagate on every rising edge of the CI pin. The
information in the shift registers is latched on a rising edge of the
Latch In (LI) pin. The latched data remains latched on a rising
Output Enable In (OEI) signal.
Output Buffers
The A6280 is designed to allow daisy chaining many A6280s
together. It has the ability to pass the clock, data, latch, and out-
put enable signals from one A6820 to the next without any loss of
data due to duty cycle skewing or signal degradation.
The A6820 is equipped with output buffers that allow the data
signals to travel over long distances through strings of A6280s
without the need for extra driving hardware. The A6280 drives
these signals to TTL levels. Each of the A6280 inputs have a cor-
responding buffered output:
• Clock In (CI) pin to Clock Out (CO) pin
• Latch In (LI) pin to Latch Out (LO) pin
• Output Enable In (OEI) pin to Output Enable Out (OEO) pin
• Serial Data In (SDI) pin to Serial Data Out (SDO) pin


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