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CAT14004 Datasheet(PDF) 6 Page - Catalyst Semiconductor

Part No. CAT14004
Description  Voltage Supervisor with I2C Serial CMOS EEPROM
Download  14 Pages
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Maker  CATALYST [Catalyst Semiconductor]
Homepage  http://www.catalyst-semiconductor.com
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CAT14004 Datasheet(HTML) 6 Page - Catalyst Semiconductor

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CAT140xx
Doc. No. 1117 Rev. A
6
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
EMBEDDED EEPROM OPERATION
The CAT140xx supports the Inter-Integrated Circuit
(I
2C) Bus data transmission protocol, which defines a
device that sends data to the bus as a transmitter and
a device receiving data as a receiver. Data flow is
controlled by a Master device, which generates the
serial clock and all START and STOP conditions. The
CAT140xx acts as a Slave device. Master and Slave
alternate as either transmitter or receiver.
I
2C BUS PROTOCOL
The I
2C bus consists of two ‘wires’, SCL and SDA.
The two wires are connected to the VCC supply via
pull-up resistors. Master and Slave devices connect to
the 2-wire bus via their respective SCL and SDA pins.
The transmitting device pulls down the SDA line to
‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while
SCL is HIGH will be interpreted as a START or STOP
condition (Figure 3). The START condition precedes
all commands. It consists of a HIGH to LOW transition
on SDA while SCL is HIGH. The START acts as a
‘wake-up’ call to all receivers. Absent a START, a
Slave will not respond to commands. The STOP
condition completes all commands. It consists of a
LOW to HIGH transition on SDA while SCL is HIGH.
START
The START condition precedes all commands.
It consists of a HIGH to LOW transition on SDA while
SCL is HIGH. The START acts as a ‘wake-up’ call to
all receivers. Absent a START, a Slave will not
respond to commands.
STOP
The STOP condition completes all commands.
It consists of a LOW to HIGH transition on SDA while
SCL is HIGH. The STOP starts the internal Write cycle
(when following a Write command) or sends the
Slave into standby mode (when following a Read
command).
Device Addressing
The Master initiates data transfer by creating a
START condition on the bus. The Master then
broadcasts an 8-bit serial Slave address. For normal
Read/Write operations, the first 4 bits of the Slave
address are fixed at 1010 (Ah). The next 3 bits are
used as programmable address bits when cascading
multiple devices and/or as internal address bits. The
last bit of the slave address, R/W, specifies whether a
Read (1) or Write (0) operation is to be performed.
The 3 address space extension bits are assigned as
illustrated in Figure 4. A2, A1 and A0 must match the
state of the external address pins, and a10, a9 and a8
are internal address bits.
Acknowledge
After processing the Slave address, the Slave
responds with an acknowledge (ACK) by pulling down
the SDA line during the 9
th clock cycle (Figure 5). The
Slave will also acknowledge the address byte and
every data byte presented in Write mode. In Read
mode the Slave shifts out a data byte, and then
releases the SDA line during the 9
th clock cycle. As
long as the Master acknowledges the data, the Slave
will continue transmitting. The Master terminates the
session by not acknowledging the last data byte
(NoACK) and by issuing a STOP condition. Bus timing
is illustrated in Figure 6.


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