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TMS470R1VF48C Datasheet(PDF) 6 Page - Texas Instruments |
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TMS470R1VF48C Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 67 page  TMS470R1VF48C/VF48B 16/32-BIT RISC FLASH MICROCONTROLLERS SPNS093D – MAY 2004 – REVISED FEBRUARY 2006 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251-1443 device characteristics The VF48x device is a derivative of the F05 system emulation device SE470R1VB8AD. Table 1 identifies all the characteristics of the VF48x device except the SYSTEM and CPU, which are generic. Table 1. Device Characteristics CHARACTERISTICS DEVICE DESCRIPTION TMS470R1VF48X COMMENTS FOR VF48X MEMORY For the number of memory selects on this device, see the Memory Selection Assignment table (Table 2). INTERNAL MEMORY Pipeline/Non-Pipeline 1M-Byte flash (VF48C only) 768K-byte flash (VF48B only) 64K-Byte SRAM (VF48C only) 48K-byte SRAM (VF48B only) Memory Security Module (MSM) JTAG Security Module Flash is pipeline-capable. The VF48C RAM is implemented in one 64K array selected by two memory-select signals (see the Memory Selection Assignment table, Table 2). The VF48B RAM is implemented in one 48K array selected by two memory-select signals (see the Memory Selection Assignment table, Table 2). PERIPHERALS For the device-specific interrupt priority configurations, see the Interrupt Priority Table (Table 5). And for the 1K peripheral address ranges and their peripheral selects, see the VF48x Peripherals, System Module, and Flash Base Addresses table (Table 3). CLOCK FMZPLL Frequency-modulated zero-pin PLL has no external loop filter pins. Expansion Bus EBM Expansion bus module with 42 pins. Supports 8- and 16-bit memories. See Table 6 for details. GENERAL-PURPOSE I/Os 46 I/O Port A has 8 external pins, Port B has only 1 external pin, Port C has 5 external pins, Port D has 6 external pins, Ports E, F, and G each have 8 external pins, and Port H has 2 external pins. ECP YES SCI 3 (3-pin) CAN (HECC and/or SCC) 2 HECC Two high-end CAN controllers SPI (5-pin, 4-pin or 3-pin) 2 (5-pin) I2C 5 HET with XOR Share 12 I/O The high-resolution (HR) SHARE feature allows even-numbered HR pins to share the next higher odd-numbered HR pin structures. This HR sharing is independent of whether or not the odd pin is available externally. If an odd pin is available externally and shared, then the odd pin can only be used as a general-purpose I/O. For more information on HR SHARE, see theTMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199). HET RAM 64-Instruction Capacity MibADC 10-bit, 12-channel 64-word FIFO Both the logic and registers for a full 16-channel MibADC are present. CORE VOLTAGE 1.8 V I/O VOLTAGE 3.3 V PINS 144 PACKAGES PGE |
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