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DSP56F826D Datasheet(PDF) 7 Page - Motorola, Inc |
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DSP56F826D Datasheet(HTML) 7 Page - Motorola, Inc |
7 / 44 page Introduction DSP56F826 Preliminary Technical Data 7 Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled. Exceptions: 1. When a pn is owned by GPIO, then the pull-up may be disabled under software control. 2. TCK has a weak pull-down circuit always active. Signal Name Pin No. Type Description A0 24 Output Address Bus—A0–A7 specify the address for external program or data memory accesses. Port E GPIO—These eight General Purpose I/O (GPIO) pins can be individually programmed as input or output pins. After reset, the default state is Address Bus. A1 23 Output A2 22 Output A3 21 Output A4 18 Output A5 17 Output A6 16 Output A7 GPIOE0– GPIOE7 15 Output Input/Output A8 14 Output Address Bus—A8–A15 specify the address for external program or data memory accesses. Port A GPIO—These eight General Purpose I/O (GPIO) pins can be individually programmed as input or output pins. After reset, the default state is Address Bus. A9 13 Output A10 12 Output A11 11 Output A12 10 Output A13 9 Output A14 8 Output A15 GPIOA0– GPIOA7 7Output Input/Output |
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