 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
DSP56800FMD Datasheet(PDF) 11 Page - Motorola, Inc |
|
||||||||||||||||||||||||||||||
DSP56800FMD Datasheet(HTML) 11 Page - Motorola, Inc |
|
|
11 / 44 page  Introduction DSP56F826 Preliminary Technical Data 11 RESET 45 Input Reset—This input is a direct hardware reset on the processor. When RESET is asserted low, the DSP is initialized and placed in the Reset state. A Schmitt trigger input is used for noise immunity. When the RESET pin is deasserted, the initial chip operating mode is latched from the external boot pin. The internal reset signal will be deasserted synchronous with the internal clocks, after a fixed number of internal clocks. To ensure complete hardware reset, RESET and TRST should be asserted together. The only exception occurs in a debugging environment when a hardware DSP reset is required and it is necessary not to reset the OnCE/ JTAG module. In this case, assert RESET, but do not assert TRST. RXD0 MOSI0 96 Input Input/ Output Receive Data (RXD0)— receive data input SPI Master Out/Slave In—This serial data pin is an output from a master device, and an input to a slave device. The master device places data on the MOSI line one half-cycle before the clock edge the slave device uses to latch the data. After reset, the default state is SCI input. RXD1 SS0 92 Input Input Receive Data (RXD1)— receive data input SPI Slave Select—In maste mode, this pin is used to arbitrate multiple masters. In slave mode, this pin is used to select the slave. After reset, the default state is SCI input. SCLK GPIOF4 84 Input/Output Input/Output SPI Serial Clock—In master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. Port F GPIO—This General Purpose I/O (GPIO) pin can be individually programmed as input or output. After reset, the default state is SCLK. SRCK GPIOC2 53 Input/Output Input/Output SSI Serial Receive Clock (STCK)—This bidirectional pin provides the serial bit rate clock for the Receive section of the SSI. The clock signal can be continuous or gated and can be used by both the transmitter and receiver in synchronous mode. Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of being individually programmed as input or output. After reset, the default state is GPIO input. Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled. Exceptions: 1. When a pn is owned by GPIO, then the pull-up may be disabled under software control. 2. TCK has a weak pull-down circuit always active. Signal Name Pin No. Type Description |
Similar Part No. - DSP56800FMD |
|
Similar Description - DSP56800FMD |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
