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74AUP1G57GF Datasheet(PDF) 4 Page - NXP Semiconductors |
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74AUP1G57GF Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 22 page 74AUP1G57_1 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Preliminary data sheet Rev. 01.00 — 16 January 2006 4 of 22 Philips Semiconductors 74AUP1G57 Low power configurable multiple function gate 7.2 Pin description 8. Functional description 8.1 Function table [1] H = HIGH voltage level; L = LOW voltage level. 8.2 Logic configurations Table 4: Pin description Symbol Pin Description B 1 data input B GND 2 ground (0 V) A 3 data input A Y 4 data output Y VCC 5 supply voltage C 6 data input C Table 5: Function table [1] Input Output C B A Y LLLH LLH L LH LH L HHL H LLL HL HL HHL H HHHH Table 6: Function selection table Logic function Figure 2-input AND see Figure 5 2-input AND with both inputs inverted see Figure 8 2-input NAND with inverted input see Figure 6 and 7 2-input OR with inverted input see Figure 6 and 7 2-input NOR see Figure 8 2-input NOR with both inputs inverted see Figure 5 2-input XNOR see Figure 9 Inverter see Figure 10 Buffer see Figure 11 |
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