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OPA3684 Datasheet(PDF) 20 Page - Burr-Brown (TI) |
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OPA3684 Datasheet(HTML) 20 Page - Burr-Brown (TI) |
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20 / 26 page  OPA3684 20 SBOS241A www.ti.com While the last term, the inverting bias current error, is dominant in this low-gain circuit, the input offset voltage will become the dominant DC error term as the gain exceeds 5V/V. Where improved DC precision is required in a high- speed amplifier, consider the OPA656 unity gain stable and OPA657 high-gain bandwidth JFET input op amps. DISABLE OPERATION The OPA3684 provides an optional disable feature on each channel that may be used to reduce system power when channel operation is not required. If the V DIS control pin is left unconnected, each channel of the OPA3684 will operate normally. To disable, the control pin must be asserted low. Figure 13 shows a simplified internal circuit for the disable control feature. 25k Ω 250k Ω 40k Ω I S Control –V S +V S V DIS Q1 In normal operation, base current to Q1 is provided through the 250k Ω resistor while the emitter current through the 40kΩ resistor sets up a voltage drop that is inadequate to turn on the two diodes in Q1’s emitter. As V DIS is pulled low, additional current is pulled through the 40k Ω resistor eventu- ally turning on these two diodes ( ≈ 30µA). At this point, any further current pulled out of V DIS goes through those diodes holding the emitter-base voltage of Q1 at approximately 0V. This shuts off the collector current out of Q1, turning the amplifier off. The supply current in the disable mode are only those required to operate the circuit of Figure 13. When disabled, the output and input nodes go to a high impedance state. If the OPA3684 is operating in a gain of +1 (with a 800 Ω feedback resistor still required for stability), this will show a very high impedance (1.7pF || 1M Ω) at the output and exceptional signal isolation. If operating at a gain greater than +1, the total feedback network resistance (RF + RG) will appear as the impedance looking back into the output, but the circuit will still show very high forward and reverse isolation. If configured as an inverting amplifier, the input and output will be connected through the feedback network resistance (RF + RG) giving relatively poor input to output isolation. Each channel of the OPA3684 provides very high power gain on low quiescent current levels. When disabled, internal high impedance nodes discharge slowly which, with the excep- tional power gain provided, give a self powering characteris- tic that leads to a slow turn off characteristic. Typical full turn- off times to rated 100 µA disabled supply current are 4ms. Turn-on times are very fast—less than 40ns. The circuit of Figure 13 will control the disable feature using standard 5V CMOS or TTL level signals when the OPA3684 is operated on ±5V or single +5V supplies. Since this circuit is really a current mode control, disable operation for a single +12V supply should be implemented using an open collector logic family. THERMAL ANALYSIS The OPA3684 will not require external heatsinking for most applications. Maximum desired junction temperature will set the maximum allowed internal power dissipation as de- scribed below. In no case should the maximum junction temperature be allowed to exceed 175 °C. Operating junction temperature (TJ) is given by TA + PD • θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 either supply voltage (for equal bipolar supplies). Under this condition PDL = VS2/(4 • RL) where RL includes feedback network loading. Note that it is the power in the output stage and not into the load that determines internal power dissipation. As an absolute worst-case example, compute the maximum TJ using an OPA3684IDBQ (SSOP-16 package) in the circuit of Figure 1 operating at the maximum specified ambient temperature of +85 °C with all channels driving a grounded 100 Ω load. PD = 10V • 5.6mA + 3 • (52 /(4 • (100Ω 1.6kΩ))) = 255mW Maximum TJ = +85°C + (0.255W • 100°C/W) = 111°C. This maximum operating junction temperature is well below most system level targets. Most applications will be lower than this since an absolute worst-case output stage power was assumed in this calculation with all 3 channels running maximum output power simultaneously. FIGURE 13. Simplified Disable Control Circuit. |
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Similar Description - OPA3684 |
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