SN74GTLPH16927

18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER

WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS

SCES413 – OCTOBER 2002

11

POST OFFICE BOX 655303

skew characteristics over recommended ranges of supply voltage and operating free-air

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

FSTA

TEST

CONDITIONS

MIN

MAX

UNIT

tsk(LH)‡

SYSCLK

B

0.5

ns

tsk(HL)‡

SYSCLK

B

0.5

ns

‡

SSCLK

→ B

VCC = 3.15 V, T = 85°C

3.4

4.7

tsk(LH)‡

SYSCLK

SSCLK

→ Bn

(see Figure 2)

GND

VCC = 3.3 V, T = 25°C

3.2

4.5

ns

(see Figure 2)

3.1

4.4

‡

SSCLK

→ B

VCC = 3.15 V, T = 85°C

3.2

4.6

tsk(HL)‡

SYSCLK

SSCLK

→ Bn

(see Figure 2)

GND

VCC = 3.3 V, T = 25°C

2.8

4.1

ns

(see Figure 2)

2.4

3.7

‡

SSCLK

→ B

VCC = 3.15 V, T = 85°C

7.1

8.9

tsk(LH)‡

SYSCLK

SSCLK

→ Bn

(see Figure 2)

VCC

VCC = 3.3 V, T = 25°C

6.6

8.4

ns

(see Figure 2)

6.3

8

‡

SSCLK

→ B

VCC = 3.15 V, T = 85°C

7.2

9

tsk(HL)‡

SYSCLK

SSCLK

→ Bn

(see Figure 2)

VCC

VCC = 3.3 V, T = 25°C

6.5

8.2

ns

(see Figure 2)

6

7.6

tsk(t)‡

SYSCLK

B

1.3

ns

tsk(prLH)§

SYSCLK

B

1.8

ns

tsk(prHL)§

SYSCLK

B

2.8

ns

† Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device.

‡ tsk(LH)/tsk(HL) and tsk(t) – Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all

outputs with the same packaged device. The specifications are given for specific worst-case VCC and temperature. The specifications apply to

any outputs switching in the same direction, either high to low [tsk(HL)], low to high [tsk(LH)], or in opposite directions, both low to high and high

to low [tsk(t)].

§ tsk(prLH) or tsk(prHL) – Part-to-part skew is designed as the absolute value of the difference between the actual propagation delay for all outputs

from device to device. The parameter is specified for a specific worst-case VCC and temperature. Furthermore, these values are provided by

TI SPICE simulations.