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VSC8111 Datasheet(PDF) 3 Page - Vitesse Semiconductor Corporation

Part No. VSC8111
Description  ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation
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Maker  VITESSE [Vitesse Semiconductor Corporation]
Homepage  http://www.vitesse.com
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VSC8111 Datasheet(HTML) 3 Page - Vitesse Semiconductor Corporation

 
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G52142-0, Rev 4.2
© VITESSE SEMICONDUCTOR CORPORATION
Page 3
8/31/98
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8111
ATM/SONET/SDH 155/622 Mb/s Transceiver
Mux/Demux with Integrated Clock Generation
Receive Section
High speed Non-Return to Zero (NRZ) serial data at 155Mb/s or 622Mb/s are received by the RXDATAIN
inputs. RXDATAIN is clocked in on the rising edge of RXCLKIN+. See Figure 2. The serial data is converted to
byte-wide parallel data and presented on RXOUT[7:0] pins. A divide-by-8 version of the high-speed clock
(RXLSCKOUT) should be used to synchronize the byte-serial RXOUT[7:0] data with the receive portion of the
UNI device.
The receive section also includes frame detection and recovery circuitry which detects the SONET/SDH
frame, aligns the received serial data on byte boundaries, and initiates a frame pulse on FP coincident with the
byte aligned data. The frame recovery is initiated when OOF is held high which must occur at least 4 byte clock
cycles before the A1A2 boundary. The OOF input control is a level-sensitive signal, and the VSC8111 will con-
tinually perform frame detection and recovery as long as this pin is held high even if 1 or more frames has been
detected. Frame detection and recovery occurs when a series of three A1 bytes followed by three A2 bytes has
been detected. The parallel output data on RXOUT[7:0] will be byte aligned starting on the third A2 byte. When
a frame is detected, a single byte clock period long pulse is generated on FP which is synchronized with the
byte-aligned third A2 byte on RXOUT[7:0]. The frame detector sends an FP pulse only if OOF is high or if a
frame was detected while OOF was being pulled low.
Figure 2: Data and Clock Receive Block Diagram
Loss of Signal
During a LOS condition, the VSC8111 forces the receive data low which is an indication for any downstream
equipment that an optical interface failure has occurred. The receive section is clocked by the transmit section’s
DQ
DQ
DQ
0
1
Divide-by-8
CMU
DQ
PM5355
DQ
RXOUT[7:0]
FP
RXLSCKOUT
VSC8111
RXDATAIN+
RXDATAIN-
RXCLKIN+
RXCLKIN-
LOSPOL
LOSTTL
1:8 Serial
to Parallel


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