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VSC8111 Datasheet(PDF) 5 Page - Vitesse Semiconductor Corporation

Part No. VSC8111
Description  ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation
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Maker  VITESSE [Vitesse Semiconductor Corporation]
Homepage  http://www.vitesse.com
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VSC8111 Datasheet(HTML) 5 Page - Vitesse Semiconductor Corporation

 
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G52142-0, Rev 4.2
© VITESSE SEMICONDUCTOR CORPORATION
Page 5
8/31/98
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC8111
ATM/SONET/SDH 155/622 Mb/s Transceiver
Mux/Demux with Integrated Clock Generation
lel to serial conversion of the low speed data (TXIN [7:0]) is selected and converted back to parallel data in the
receiver section and presented at the low speed parallel outputs (RXOUT [7:0]). See Figure 4. The internally
generated 155MHz/622MHz clock is used to generate the low speed receive clock output (RXLSCKOUT). In
Equipment Loopback mode the transmit data (TXIN [7:0]) is serialized and presented at the high speed output
(TXDATAOUT) along with the high speed transmit clock (TXCLKOUT) which is generated by the on board
clock multiplier unit.
Figure 4: Equipment Loopback Data Path
Split Loopback
Equipment and facility loopback modes can be enabled simultaneously. See descriptions for equipment and
facility loop modes above. The only change is, since they are both active, RXDATAIN will not be deserialized
and presented to RXOUT[0:7] and TXIN[0:7] will not be serialized and present to TXDATAOUT.
Figure 5: Split Loopback Datapath
DQ
D
Q
1:8
Serial to
Parallel
Q
D
RXDATAIN
TXDATAOUT
RXOUT[7:0]
Q
D
8:1
Parallel to
Serial
TXIN[7:0]
÷ 8
PLL
÷ 8
RXLSCKOUT
TXLSCKIN
TXLSCKOUT
TXCLKOUT
0
1
EQULOOP
0
1
RXCLKIN
D
Q
1:8
Serial to
Parallel
RXOUT[7:0]
Q
D
8:1
Parallel to
Serial
TXIN[[7:0]
RXLSCKOUT
DQ
Q
D
RXDATAIN
TXDATAOUT
0
1
TXCLKOUT
FACLOOP
RXCLKIN
0
1
÷ 8
PLL
TXLSCLKIN
0
1
EQULOOP
0
1


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