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TAS5036B Datasheet(PDF) 38 Page - Texas Instruments |
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TAS5036B Datasheet(HTML) 38 Page - Texas Instruments |
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38 / 56 page  System Procedures for Initialization, Changing Data Rates, and Switching Between Master and Slave Modes 32 SLES073—February 2003 TAS5036B MCLK MUTE Terminal DBSPD Terminal Change from a 96-kHz data rate MCLK_IN = 24.576 MHz Clock transition Change to a 48-kHz data rate MCLK_IN = 12.288 MHz Volume ramp up 42 – 65 ms > 5 ms < 2 ms < 2 ms Volume ramp down 42 – 65 ms Set within 2 ms of transition Figure 4–3. Changing the Data Sample Rate Using the DBSPD Terminal MCLK MUTE Terminal Change from a 96-kHz data rate MCLK_IN = 24.576 MHz Clock transition Change to a 48-kHz data rate MCLK_IN = 12.288 MHz Volume ramp up 42 – 65 ms > 5 ms < 2 ms < 2 ms Volume ramp down 42 – 65 ms Set data rate via I2C register X02D7 and D6 ERR_RCVRY Terminal Hold ERR_RCVRY low to give additional timeset registers Figure 4–4. Changing the Data Sample Rate Using the I2C However, if the master clock input can encounter a high clock or low clock period of less than 20 ns, then RESET should be applied during this time. There are two recommended control procedures for this case, depending upon whether the DBSPD terminal or the serial control interface is used. These control sequences are shown in Figure 4–5 and Figure 4–6. Because this sequence employs the RESET terminal the internal register settings are set to the default values. |
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