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IDTCV110L Datasheet(PDF) 1 Page - Integrated Device Technology

Part No. IDTCV110L
Description  PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDTCV110L Datasheet(HTML) 1 Page - Integrated Device Technology

 
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COMMERCIALTEMPERATURERANGE
IDTCV110L
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
1
IDT CONFIDENTIAL
DECEMBER 2004
IDTCV110L
COMMERCIAL TEMPERATURE RANGE
PROGRAMMABLE FLEXPC
CLOCK FOR P4 PROCESSOR
XTAL
Osc Amp
SM Bus
Controller
Control
Logic
CPU CLK
Output Buffers
Stop Logic
X1
X2
SDATA
SCLK
VTT_PWRGD#/PD
FSA.B.C
IREF
CPU[1:0]
REF
CPU_ITP/SRC7
PLL1
SSC
N Programmable
ITP_EN
SRC CLK
Output Buffer
Stop Logic
48MHz/96MHz
Output BUffer
IREF
SRC[6:1]
48MHz
DOT96
PLL2
SSC
N Programmable
PLL3
PCI[5:0], PCIF[2:0]
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
© 2004 Integrated Device Technology, Inc.
DSC-6534/5
FEATURES:
• One high precision PLL for CPU, SSC, and N programming
• One high precision PLL for SRC/PCI/SATA, SSC, and N
programming
• One high precision PLL for 96MHz/48MHz
• Band-gap circuit for differential outputs
• Support spread spectrum modulation, down spread 0.5%
• Support SMBus block read/write, index read/write
• Selectable output strength for REF
• Allows for CPU frequency to change to a higher frequency for
maximum system computing power
• Available in SSOP package
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
IDTCV110L is a 56 pin clock device. The CPU output buffer is designed to
support up to 400MHz processor. This chip has three PLLs inside for CPU/
SRC/PCI,SATA,and48MHz/DOT96IOclocks. OnededicatedPLLforSerial
ATA clock provides high accuracy frequency. This device also implements
Band-gapreferencedIREF toreducetheimpactofVDD variationondifferential
outputs, which can provide more robust system performance.
StaticPLLfrequencydivideerrorcanbeaslowas36ppm,worsecase114
ppm,providinghighaccuracyoutputclock. EachCPU/SRC/PCI,SATAclock
has its own Spread Spectrum selection, which allows for isolated changes
instead of affecting other clock groups.
OUTPUTS:
• 2*0.7V current –mode differential CPU CLK pair
• 6*0.7V current –mode differential SRC CLK pair, one dedicated
for SATA
• One CPU_ITP/SRC selectable CLK pair
• 9*PCI, 3 free running, 33.3MHz
• 1*96MHz,1*48MHz
• 1*REF
KEY SPECIFICATION:
• CPU/SRC CLK cycle to cycle jitter < 85ps
• SATA CLK cycle to cycle jitter < 85ps
• PCI CLK cycle to cycle jitter < 250ps
• Static PLL frequency divide error < 114 ppm
• Static PLL frequency divide error for 48MHz < 5 ppm


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