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IDTCV110L Datasheet(PDF) 3 Page - Integrated Device Technology

Part No. IDTCV110L
Description  PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
Download  16 Pages
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDTCV110L Datasheet(HTML) 3 Page - Integrated Device Technology

 
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COMMERCIALTEMPERATURERANGE
IDTCV110L
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
3
IDT CONFIDENTIAL
PIN DESCRIPTION
Pin Number
Name
Type
Description
1VDD_PCI
PWR
3.3V
2VSS_PCI
GND
GND
3
PCI3
OUT
PCI clock
4
PCI4
OUT
PCI clock
5
PCI5
OUT
PCI clock
6VSS_PCI
GND
GND
7VDD_PCI
PWR
3.3V
8
PCIF0/ITP_EN
I/O
PCI clock, free running. CPU2 select (sampled on VTT_PWRGD# assertion) HIGH = CPU2.
9
PCIF1
OUT
PCI clock, free running
10
PCIF2
OUT
PCI clock, free running
11
VDD48
PWR
3.3V
12
USB48
OUT
48MHz clock
13
VSS48
GND
GND
14
DOT96
OUT
96MHz0.7currentmodedifferentialclockoutput
15
DOT96#
OUT
96MHz0.7currentmodedifferentialclockoutput
16
FSB/TEST_MODE
IN
CPU frequency selection. Selects REF/N or Hi-Z when in test mode, Hi-Z = 1, REF/N = 0.
17
VTT_PWRGD#/PD
IN
Level-sensitive strobe used to latch the FSA, FSB, FSC/TEST_SEL, and PCIF0/ITP_EN inputs. After
VTT_PWRGD# assertion, becomes a real-time input for asserting power down. (Active HIGH)
18
FSA
IN
CPU frequency selection
19
SRC1
OUT
Differentialserialreferenceclock
20
SRC1#
OUT
Differentialserialreferenceclock
21
VDD_SRC
PWR
3.3V
22
SRC2
OUT
Differentialserialreferenceclock
23
SRC2#
OUT
Differentialserialreferenceclock
24
SRC3
OUT
Differentialserialreferenceclock
25
SRC3#
OUT
Differentialserialreferenceclock
26
SRC4
OUT
Differentialserialreferenceclock
27
SRC4#
OUT
Differentialserialreferenceclock
28
VDD_SRC
PWR
3.3V
29
VSS_SRC
GND
GND
30
SRC5#
OUT
Differentialserialreferenceclock
31
SRC5
OUT
Differentialserialreferenceclock
32
SRC6#
OUT
Differentialserialreferenceclock
33
SRC6
OUT
Differentialserialreferenceclock
34
VDD_SRC
PWR
3.3V
35
CPU2_ITP#/SRC7#
OUT
Selectable CPU or SRC differential clock output. ITP_EN = 0 at VTT_PWRGD# assertion = SRC7#.
36
CPU2_ITP/SRC7
OUT
Selectable CPU or SRC differential clock output. ITP_EN = 0 at VTT_PWRGD# assertion = SRC7.
37
VDDA
PWR
3.3V
38
VSSA
GND
GND
39
IREF
OUT
Referencecurrentfordifferentialoutputbuffer
40
CPU1#
OUT
Host0.7currentmodedifferentialclockoutput
41
CPU1
OUT
Host0.7currentmodedifferentialclockoutput
42
VDD_CPU
PWR
3.3V


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