CY7C1353 datasheet(10/13 Pages) CYPRESS

Part #	CY7C1353

Description	256Kx18 Flow-Through SRAM with NoBL Architecture

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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CY7C1353

10

Switching Waveforms

Read/Write Waveforms

CEN

CLK

ADDRESS

CE

WE

Data-

In/Out

tCYC

tCH tCL

tCENS

tCENH

RA1

tAH

tAS

tWS tWH

tCES

tCEH

tCDV

Q4

Q1

= DON’T CARE

= UNDEFINED

WE is the combination of WE & BWSx to define a Write Cycle (see Write Cycle Description Table).

Out

D2

In

D5

In

Out

WA2

RA3

RA4

WA5

RA6

RA7

tCLZ

tDOH

Q3

Out

tCHZ

CE is the combination of CE1, CE2, and CE3. All Chip Selects need to be active in order to select

the device. Any Chip Select can deselect the device. RAx stands for Read Address X, WAx stands for

Device

originally

deselected

Write Address X, Dx stands for Data-in X, Qx stands for Data-out X.

Q7

Out

tCHZ

tCENS

tCENH

tDOH

Q6

Out

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