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UG14 Datasheet(PDF) 3 Page - ATMEL Corporation |
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UG14 Datasheet(HTML) 3 Page - ATMEL Corporation |
3 / 7 page UG Series 5–3 Rev. B – 25 May. 98 Core switching current protection This noise disturbance is caused by a large number of gates switching simultaneously. To allow this without impacting the functionality of the circuit, three new features have been added: Some decoupling capacitors are integrated directly on the silicon to reduce the power supply drop. A power supply network has been implemented in the matrix. This solution lessens the parasitic elements such as inductance and resistance and constitutes an artificial VDD and VSS plane. One mesh of the network supplies approximately 150 cells. A low-pass filter has been added between the core and the inputs of the output buffers. This limits the transmission of the noise coming from the ground or the VDD supply of the core via the output buffers. Absolute Maximum Ratings Supply Voltage (VDD) –0.5 V to 7.0 V . . . . . . . . . . . . . . . . . . . . . . . . Input Voltage (VIN) –0.5 V to VDD + 7.0 V . . . . . . . . . . . . . . . . . . . Storage Temperature –65 to 150 _C . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Range VDD 5 V "5% or 3.3 V "5% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Temperature Commercial 0 to 70 _C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Industrial –40 to 85 _C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Military –55 to 125 _C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics Parameter Symbol Base Part TA = Commercial Min Typ Max Unit VOH IOH = 24, 12, 6, 3 depending on buffer 2.4 Output Voltage VOL IOL = –24, –12, –6, –3 depending on buffer 0.4 VIH 2.0 V Input Voltage VIL 0.8 VIN = VSS –5 –1 VIN = VDD 1 5 Input Leakage Current IIX VIN = VSS, with pull-up –100 –40 µA VIN = VDD, with pull-down 40 100 µ Output Leakage Current IOZ VOUT = VSS or VDD –5 "1 5 VOUT = VDD 90 160 Output Short Circuit Current IOS VOUT = VSS –130 –60 mA Standby Current ICCSB VDD = 5.25 V, VIN = VSS 0.4 1 nA/Gate Operating Current IDDOP 0.3 0.4 µA/Gate/ MHz Input Capacitance CIN VDD = 5.0 V, VIN = 2.0 V 2.5 Output Capacitance COUT VOUT = 2.0 V 2 pF Notes: a. IOH = 24, 12, 6,3. Selection determined by FPGA or PLD data sheet requirements. |
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