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CS5016-BL16 Datasheet(PDF) 31 Page - Cirrus Logic |
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CS5016-BL16 Datasheet(HTML) 31 Page - Cirrus Logic |
31 / 46 page sampling rate, a tone will appear as the clock fre- quency aliases into the baseband. The tone frequency can be calculated using the equation below and could be selectively filtered in soft- ware using DSP techniques. ftone = (N fs - fclk) where N = fclk/fs rounded to the nearest integer The magnitude of clock feedthrough depends on the master clock conditions and the source im- pedance applied to the analog input. When operating with the CS5014/16’s internally gener- ated clock, the CLKIN input is grounded and the dominant source of coupling is through the de- vice’s substrate. As shown in Figure 35, a typical CS5014/16 operating with their internal oscillator at 2 MHz and 50 Ω of analog input source im- pedance will exhibit only 15 µV rms of clock feedthrough. However, if a 2 MHz external clock is applied to CLKIN under the same conditions, feedthrough increases to 25 µV rms. Feedthrough also increases with clock frequency; a 4 MHz clock yields 40 µV rms. Clock feedthrough can be reduced by limiting the source impedance applied at the analog input. As shown in Figure 35, reducing source impedance from 50 Ω to 25 Ω yields a 15 µV rms reduction in feedthrough. Therefore, when operating the CS5014/16 with high-frequency external master clocks, it is important to minimize source imped- ance applied to the CS5014/16’s input. Also, the overall effect of clock feedthrough can be minimized by maximizing the input range and LSB size. The reference voltage applied to VREF can be maximized, and the CS5014/16 can be op- erated in bipolar mode which inherently doubles the LSB size over the unipolar mode. Differences between the CS5012A and the CS5012 The differences between the CS5012A and the CS5012 are tabulated in Table 3. The CS5012 is a short-cycled version of the CS5016 A/D con- verter and includes the same 18-bit calibration circuitry. This calibration circuitry sets the cali- bration resolution of the CS5012 at 1/64th of an LSB and achieves the near perfect differential linearity performance illustrated by the CS5012 DNL plot in Figure 15. The CS5012A calibration circuitry was modified to provide calibration to 15-bit resolution therefore achieving calibration to 1/8 of an LSB. This reduction in calibration resolution for the CS5012A reduces the time re- quired to calibrate the device (see Table 3) and reduces the size of the total array capacitance. The reduced array capacitance improves the high frequency performance by allowing higher slew rate in the input circuitry. Table 3 documents some other improvements in- cluded in the CS5012A. The burst mode calibration was made functional, although it should not be used. The device was also modified so the EOC signal goes low at the end of a reset calibration in either microprocessor or microproc- essor-independent mode. The CS5012A was modified to maintain a throughput rate of 64 CLKIN cycles in loopback mode for all frequen- cies of CLKIN. Schematic & Layout Review Service Confirm Optimum Schematic & Layout Before Building Your Board. For Our Free Review Service Call Applications Engineering. Call: (512) 445-7222 CS5012A, CS5014, CS5016 DS14F6 2-37 |
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