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LH28F160BJE-TTL90 Datasheet(PDF) 6 Page - Sharp Electrionic Components

Part No. LH28F160BJE-TTL90
Description  16M (x8/x16) Flash Memory
Download  46 Pages
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Maker  SHARP [Sharp Electrionic Components]
Homepage  http://sharp-world.com/
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LH28F160BJE-TTL90 Datasheet(HTML) 6 Page - Sharp Electrionic Components

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LHF16J02
4
Rev. 1.26
The access time is 90ns (tAVQV) over the operating
temperature range (0°C to +70°C) and VCC supply voltage
range of 2.7V-3.6V.
The Automatic Power Savings (APS) feature substantially
reduces active current when the device is in static mode
(addresses not switching). In APS mode, the typical ICCR
current is 2µA (CMOS) at 3.0V VCC.
When CE# and RP# pins are at VCC, the ICC CMOS
standby mode is enabled. When the RP# pin is at GND,
reset
mode
is
enabled
which
minimizes
power
consumption and provides write protection. A reset time
(tPHQV) is required from RP# switching high until outputs
are valid. Likewise, the device has a wake time (tPHEL)
from RP#-high until writes to the CUI are recognized.
With RP# at GND, the WSM is reset and the status
register is cleared.
Please do not execute reprogramming "0" for the bit which
has already been programed "0". Overwrite operation may
generate unerasable bit. In case of reprogramming "0" to
the data which has been programed "1".
·Program "0" for the bit in which you want to change
data from "1" to "0".
·Program "1" for the bit which has already been
programmed "0".
For
example,
changing
data
from
"10111101"
to
"10111100" requires "11111110" programming.
1.3 Product Description
1.3.1 Package Pinout
LH28F160BJE-TTL90 Boot Block Flash memory is
available in 48-lead TSOP package (see Figure 2).
1.3.2 Block Organization
This
product
features
an
asymmetrically-blocked
architecture providing system memory integration. Each
erase block can be erased independently of the others up to
100,000 times. For the address locations of the blocks, see
the memory map in Figure 3.
Boot Blocks: The boot block is intended to replace a
dedicated
boot
PROM
in
a
microprocessor
or
microcontroller-based system. This boot block 4K words
(4,096words)
features
hardware
controllable
write-
protection to protect the crucial microprocessor boot code
from accidental modification. The protection of the boot
block is controlled using a combination of the VCCW, RP#,
WP# pins and block lock-bit.
Parameter Blocks: The boot block architecture includes
parameter blocks to facilitate storage of frequently update
small
parameters
that
would
normally
require
an
EEPROM. By using software techniques, the word-rewrite
functionality of EEPROMs can be emulated. Each boot
block component contains six parameter blocks of 4K
words (4,096 words) each. The protection of the parameter
block is controlled using a combination of the VCCW, RP#
and block lock-bit.
Main Blocks: The reminder is divided into main blocks for
data or code storage. Each 16M-bit device contains thirty-
one 32K words (32,768 words) blocks. The protection of
the main block is controlled using a combination of the
VCCW, RP# and block lock-bit.


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