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CS5016-KP32 Datasheet(PDF) 8 Page - Cirrus Logic

Part No. CS5016-KP32
Description  16, 14 & 12-Bit, Self-Calibrating A/D Converters
Download  46 Pages
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Maker  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
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CS5016-KP32 Datasheet(HTML) 8 Page - Cirrus Logic

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SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ±10%;
VA-, VD- = -5V
±10%; Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF, BW = VD+)
Parameter
Symbol
Min
Typ
Max
Units
CS5012A CLKIN Frequency:
Internally Generated:
Externally Supplied:
-7
-12
fCLK
1.75
100 kHz
100 kHz
-
-
-
-
6.4
4.0
MHz
MHz
MHz
CS5014/5016 CLKIN Frequency:
Internally Generated:
-14, -16
-28, -32
Externally Supplied:
-14, -16
-28, -32
fCLK
1.75
1
100 kHz
100 kHz
-
-
-
-
-
-
4
2
MHz
MHz
MHz
MHz
CLKIN Duty Cycle
40
-
60
%
Rise Times:
Any Digital Input
Any Digital Output
trise
-
-
-
20
1.0
-
µs
ns
Fall Times:
Any Digital Input
Any Digital Output
tfall
-
-
-
20
1.0
-
µs
ns
HOLD Pulse Width
thpw
1/fCLK+50
-
tc
ns
Conversion Time:
CS5012A
CS5014
CS5016
tc
49/fCLK+50
57/fCLK
65/fCLK
-
-
-
53/fCLK+235
61/fCLK+235
69/fCLK+235
ns
ns
ns
Data Delay Time
tdd
-
40
100
ns
EOC Pulse Width
(Note 11)
tepw
4/fCLK-20
-
-
ns
Set Up Times:
CAL, INTRLV to CS Low
A0 to CS and RD Low
tcs
tas
20
20
10
10
-
-
ns
ns
Hold Times:
CS or RD High to A0 Invalid
CS High to CAL, INTRLV Invalid
tah
tch
50
50
30
30
-
-
ns
ns
Access Times:
CS Low to Data Valid
A, B, J, K
S, T
RD Low to Data Valid
A, B, J, K
S, T
tca
tra
-
-
-
-
90
115
90
90
120
150
120
150
ns
ns
ns
ns
Output Float Delay:
K, B
CS or RD High to Output Hi-Z
T
tfd
-
-
90
90
110
140
ns
ns
Serial Clock
Pulse Width Low
Pulse Width High
tpwl
tpwh
-
-
2/fCLK
2/fCLK
-
-
ns
ns
Set Up Times:
SDATA to SCLK Rising
tss
2/fCLK-50
2/fCLK
-ns
Hold Times:
SCLK Rising to SDATA
tsh
2/fCLK-100
2/fCLK
-ns
Notes: 11. EOC remains low 4 CLKIN cycles if CS and RD are held low. Otherwise, it returns high
within 4 CLKIN cycles from the start of a data read operation or a conversion cycle.
CS5012A, CS5014, CS5016
2-14
DS14F6


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