32K x 16 Static RAM
fax id: 1075
CY7C1020V
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
October 1996 – Revised April 13, 1998
Features
• 3.3V operation (3.0V - 3.6V)
• High speed
—tAA = 10 ns
• Low active power
— 540 mW (max., 12 ns)
• Very Low standby power
—330
µW (max., “L” version)
• Automatic power-down when deselected
• Independent Control of Upper and Lower bytes
• Available in 44-pin TSOP II and 400-mil SOJ
Functional Description
The CY7C1020V is a high-performance CMOS static RAM or-
ganized as 32,768 words by 16 bits. This device has an auto-
matic power-down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking chip enable
(CE) and write enable (WE) inputs LOW. If byte low enable
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A14). If byte high enable (BHE) is LOW, then data from
I/O pins (I/O9 through I/O16) is written into the location speci-
fied on the address pins (A0 through A14).
Reading from the device is accomplished by taking chip en-
able (CE) and output enable (OE) LOW while forcing the write
enable (WE) HIGH. If byte low enable (BLE) is LOW, then data
from the memory location specified by the address pins will
appear on I/O1 to I/O8. If byte high enable (BHE) is LOW, then
data from memory will appear on I/O9 to I/O16. See the truth
table at the back of this datasheet for a complete description
of read and write modes.
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1020V is available in standard 44-pin TSOP type II
and 400-mil-wide SOJ packages.
Selection Guide
7C1020V-10
7C1020V-12
7C1020V-15
7C1020V-20
Maximum Access Time (ns)
10
12
15
20
Maximum Operating Current (mA)
130
120
110
100
L100
90
80
70
Maximum CMOS Standby Current (mA)
1
1
1
1
L0.1
0.1
0.1
0.1
WE
Logic Block Diagram
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
14
31
32
36
35
34
33
37
40
39
38
Top View
SOJ / TSOP II
12
13
41
44
43
42
16
15
29
30
VCC
NC
NC
OE
VSS
A0
I/O16
CE
I/O3
I/O1
I/O2
BHE
NC
1020V-2
18
17
20
19
I/O4
27
28
25
26
22
21
23
24
NC
VSS
I/O7
I/O5
I/O6
I/O8
A1
A2
BLE
VCC
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
A3
A4
A5
A6
32K x 16
RAM Array
I/O1 – I/O8
A6
A5
A4
A3
A0
COLUMN DECODER
DATA IN DRIVERS
OE
A2
A1
I/O9 – I/O16
CE
WE
BLE
BHE
A 14
A 13
A 12
A 11
A 10
A9
A8
A7
1020V-1
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