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CY7C1020V Datasheet(PDF) 5 Page - Cypress Semiconductor

Part No. CY7C1020V
Description  32K x 16 Static RAM
Download  9 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1020V Datasheet(HTML) 5 Page - Cypress Semiconductor

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CY7C1020V
5
Switching Characteristics[4] Over the Operating Range (continued)
Parameter
Description
7C1020V-20
Unit
Min.
Max.
READ CYCLE
tRC
Read Cycle Time
20
ns
tAA
Address to Data Valid
20
ns
tOHA
Data Hold from Address Change
3
ns
tACE
CE LOW to Data Valid
20
ns
tDOE
OE LOW to Data Valid
9
ns
tLZOE
OE LOW to Low Z
0
ns
tLZCE
CE LOW to Low Z[6]
3ns
tHZCE
CE HIGH to High Z[5, 6]
9ns
tPU
CE LOW to Power-Up
0
ns
tPD
CE HIGH to Power-Down
20
ns
tDBE
Byte enable to Data Valid
9
ns
tLZBE
Byte enable to Low Z
0
ns
tHZBE
Byte disable to High Z
9
ns
WRITE CYCLE[7]
tWC
Write Cycle Time
20
ns
tSCE
CE LOW to Write End
12
ns
tAW
Address Set-Up to Write End
12
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-Up to Write Start
0
ns
tPWE
WE Pulse Width
12
ns
tSD
Data Set-Up to Write End
10
ns
tHD
Data Hold from Write End
0
ns
tLZWE
WE HIGH to Low Z[6]
3ns
tHZWE
WE LOW to High Z[5, 6]
9ns
tBW
Byte enable to end of write
12
ns
Switching Waveforms
Notes:
8.
Device is continuously selected. OE, CE, BHE, and/or BHE = VIL
9.
WE is HIGH for read cycle.
Read Cycle No.1
PREVIOUS DATA VALID
DATA VALID
tRC
tAA
tOHA
1020V-5
ADDRESS
DATA OUT
[8, 9]


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