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KS8995M Datasheet(PDF) 1 Page - Micrel Semiconductor

Part No. KS8995M
Description  Integrated 5-Port 10/100 Managed Switch
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Maker  MICREL [Micrel Semiconductor]
Homepage  http://www.micrel.com
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KS8995M Datasheet(HTML) 1 Page - Micrel Semiconductor

 
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December 2003
1
M9999-120403
KS8995M
Micrel
KS8995M
Integrated 5-Port 10/100 Managed Switch
Rev 1.12
General Description
The KS8995M is a highly integrated Layer-2 managed switch
with optimized BOM (Bill of Materials) cost for low port count,
cost-sensitive 10/100Mbps switch systems. It also provides
an extensive feature set such as tag/port-based VLAN, QoS
(Quality of Service) priority, management, MIB counters, dual
MII interfaces and CPU control/data interfaces to effectively
address both current and emerging Fast Ethernet applica-
tions.
The KS8995M contains five 10/100 transceivers with pat-
ented mixed-signal low-power technology, five MAC (Media
Access Control) units, a high-speed non-blocking switch
fabric, a dedicated address look-up engine, and an on-chip
frame buffer memory.
All PHY units support 10BaseT and 100BaseTX. In addition,
two of the PHY units support 100BaseFX (Ports 4 and 5).
All support documentation can be found on Micrel’s web site
at www.micrel.com.
Features
• Integrated switch with five MACs and five Fast Ethernet
transceivers fully compliant to IEEE 802.3u standard
• Shared memory based switch fabric with fully non-
blocking configuration
• 1.4Gbps high-performance memory bandwidth
• 10BaseT, 100BaseTX and 100BaseFX modes (FX in
Ports 4 and 5)
• Dual MII configuration: MII-Switch (MAC or PHY mode
MII) and MII-P5 (PHY mode MII)
• IEEE 802.1q tag-based VLAN (16 VLANs, full-range
VID) for DMZ port, WAN/LAN separation or inter-VLAN
switch links
• VLAN ID tag/untag options, per-port basis
• Programmable rate limiting 0Mbps to 100Mbps, ingress
and egress port, rate options for high and low priority,
per-port-basis
• Flow control or drop packet rate limiting (ingress port)
• Integrated MIB counters for fully compliant statistics
gathering, 34 MIB counters per port
Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com
Functional Diagram
1K look-up
Engine
Queue
Mgmnt
10/100
MAC 1
Buffer
Mgmnt
Frame
Buffers
10/100
MAC 2
10/100
MAC 3
10/100
MAC 4
10/100
MAC 5
SNI
10/100
T/Tx 1
10/100
T/Tx 2
10/100
T/Tx 3
10/100
T/Tx/Fx 4
10/100
T/Tx/Fx 5
SPI
EEPROM
I/F
LED I/F
Auto
MDI/MDIX
Auto
MDI/MDIX
Auto
MDI/MDIX
Auto
MDI/MDIX
Auto
MDI/MDIX
Control Reg I/F
KS8995M
MIB
Counters
MII-SW or SNI
LED0[5:1]
LED1[5:1]
LED2[5:1]
Control
Registers
MII-P5
MDC, MDI/O


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