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ATA6831 Datasheet(PDF) 4 Page - ATMEL Corporation

Part No. ATA6831
Description  Triple Half-bridge Driver with SP and PWM
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Maker  ATMEL [ATMEL Corporation]
Homepage  http://www.atmel.com
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ATA6831 Datasheet(HTML) 4 Page - ATMEL Corporation

 
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4
4908D–AUTO–09/06
ATA6831
3.
Functional Description
3.1
Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized
to CLK and is accepted on the falling edge of the CLK signal. The LSB (bit 0, SRR) has to be
transferred first. Execution of new input data is enabled on the rising edge of the CS signal.
When CS is high, pin DO is in tri-state condition. This output is enabled on the falling edge of
CS. Output data will change their state with the rising edge of CLK and stay stable until the next
rising edge of CLK appears. LSB (bit 0, TP) is transferred first.
Figure 3-1.
Data Transfer
SRR
LS1
HS1
LS2
HS2
LS3
HS3
nPL!
PH1
PL2
PH2
PL3
PH3
OLD
OCS
SI
CS
DI
CLK
DO
TP
S1L
S1H
S2L
S2H
S3L
S3H
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
OVl
INH
PSF
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Table 3-1.
Input Data Protocol
Bit
Input Register
Function
0SRR
Status register reset (high = reset; the bits PSF and OVL in the output
data register are set to low)
1
LS1
Controls output LS1 (high = switch output LS1 on)
2
HS1
Controls output HS1 (high = switch output HS1 on)
3
LS2
See LS1
4
HS2
See HS1
5
LS3
See LS1
6
HS3
See HS1
7
PL1
Output LS1 additionally controlled by PWM Input
8
PH1
Output HS1 additionally controlled by PWM Input
9
PL2
See PL1
10
PH2
See PH1
11
PL3
See PL1
12
PH3
See PH1
13
OLD
Open load detection (low = on)
14
OCS
Overcurrent shutdown (high = overcurrent shutdown is active)
15
SI
Software inhibit; low = standby, high = normal operation
(data transfer is not affected by the standby function because the digital
part is still powered)


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